公开(公告)号：US10566331B1

公开(公告)日：2020-02-18

申请号：US16257913

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-gil Yang ,  Sang-su Kim ,  Sun-wook Kim ,  Geum-jong Bae ,  Seung-min Song ,  Soo-jin Jeong

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02

Abstract: A semiconductor device includes: a fin-type active area extending in a first direction protruding from a substrate; a plurality of nanosheet stacked structures; a blocking film covering a part of the upper surface and one sidewall of each of a pair of nanosheet stacked structures adjacent to both sides of the fin-type active area among the plurality of nanosheet stacked structures; a gate electrode extending in a second direction intersecting the first direction on the fin-type active area, the gate electrode including a real gate electrode surrounding the plurality of nanosheets and a dummy gate electrode disposed on the blocking film; and a gate dielectric layer between the real gate electrode and the plurality of nanosheets and between the dummy gate electrode and the blocking film.

公开(公告)号：US09412816B2

公开(公告)日：2016-08-09

申请号：US14605041

申请日：2015-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-gil Yang ,  Sang-su Kim ,  Tae-yong Kwon

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device comprises at least two nanowire patterns over a substrate, wherein the at least two nanowire patterns have increasingly narrower widths as they extend away from the substrate and have different channel impurity concentrations. A gate electrode surrounds at least a part of the at least two nanowire patterns. A gate dielectric film is disposed between the at least two nanowire patterns and the gate electrode.

Abstract translation: 半导体器件在衬底上包括至少两个纳米线图案，其中当它们远离衬底延伸并且具有不同的沟道杂质浓度时，至少两个纳米线图案具有越来越窄的宽度。 栅电极围绕至少两个纳米线图案的至少一部分。 栅电介质膜设置在至少两个纳米线图案和栅电极之间。