公开(公告)号：US09412816B2

公开(公告)日：2016-08-09

申请号：US14605041

申请日：2015-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-gil Yang ,  Sang-su Kim ,  Tae-yong Kwon

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device comprises at least two nanowire patterns over a substrate, wherein the at least two nanowire patterns have increasingly narrower widths as they extend away from the substrate and have different channel impurity concentrations. A gate electrode surrounds at least a part of the at least two nanowire patterns. A gate dielectric film is disposed between the at least two nanowire patterns and the gate electrode.

Abstract translation: 半导体器件在衬底上包括至少两个纳米线图案，其中当它们远离衬底延伸并且具有不同的沟道杂质浓度时，至少两个纳米线图案具有越来越窄的宽度。 栅电极围绕至少两个纳米线图案的至少一部分。 栅电介质膜设置在至少两个纳米线图案和栅电极之间。

公开(公告)号：US10014300B2

公开(公告)日：2018-07-03

申请号：US15480669

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Tae-yong Kwon ,  Jae-young Park ,  Dong-hoon Hwang ,  Han-ki Lee ,  So-ra You

IPC: H01L29/00 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7854

Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.

公开(公告)号：US20170317084A1

公开(公告)日：2017-11-02

申请号：US15480669

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Tae-yong Kwon ,  Jae-young Park ,  Dong-hoon Hwang ,  Han-ki Lee ,  So-ra You

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/762 ,  H01L21/768 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.