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    SEMICONDUCTOR DEVICES
    1.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220139901A1

    公开(公告)日：2022-05-05

    申请号：US17338201

    申请日：2021-06-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dayeon CHO ,  Hyungock KIM ,  Sangdo PARK

    IPC: H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/392 ,  G06F30/398

    Abstract: A semiconductor device includes standard cells in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, and filler cells between ones of the standard cells. Each of the standard cells includes an active region, a gate structure that intersects the active region, source/drain regions on the active region on both sides of the gate structure, and interconnection lines. Each of the filler cells includes a filler active region and a filler gate structure that intersects the filler active region. The standard cells include first to third standard cells in first to third rows sequentially in the second direction, respectively. First interconnection lines are arranged with a first pitch, second interconnection lines are arranged with a second pitch, and third interconnection lines are arranged with a third pitch different from the first and second pitches.

    INTEGRATED CIRCUIT INCLUDING COMPLEMENTARY FIELD EFFECT TRANSISTOR
    5.
    发明申请
    INTEGRATED CIRCUIT INCLUDING COMPLEMENTARY FIELD EFFECT TRANSISTOR 有权

    公开(公告)号：US20250096138A1

    公开(公告)日：2025-03-20

    申请号：US18739664

    申请日：2024-06-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeha LEE ,  Sukjin KIM ,  Sangdo PARK ,  Yongho LEE ,  Hongmook CHOI

    IPC: H01L23/528 ,  H01L27/092

    Abstract: Provided is an integrated circuit including a complementary field effect transistor including a first transistor and a second transistor arranged in a vertical direction on a front side of a substrate, a via structure extending in the vertical direction on the second transistor and interconnecting a source/drain of the second transistor to a source/drain of the first transistor, at least one frontside power rail disposed above the first transistor in the vertical direction and transmitting a first supply voltage to the first transistor, a backside via penetrating through the substrate in the vertical direction, and at least one backside power rail disposed on a back side of the substrate and transmitting a second supply voltage to the second transistor through the backside via, wherein the first supply voltage and the second supply voltage have different voltage levels, and the first transistor and the second transistor share a gate line.

    METHOD AND APPARATUS WITH TEST RESULT RELIABILITY VERIFICATION
    6.
    发明申请
    METHOD AND APPARATUS WITH TEST RESULT RELIABILITY VERIFICATION 有权

    公开(公告)号：US20250086079A1

    公开(公告)日：2025-03-13

    申请号：US18828022

    申请日：2024-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keunseo KIM ,  Jaecheol LEE ,  Sangkyu PARK ,  Sangdo PARK ,  Dokyoung KIM ,  Minkyu YANG ,  Young LEE ,  Jinsic JANG

    IPC: G06F11/22

    Abstract: A method for verifying reliability of a test for products performed by test equipment includes: receiving result images generated from preprocessing of result data of the test, the result data of the test including labels for a plurality of scale levels and the received result images including first result images belonging to a first scale level of the plurality of scale levels and second result images belonging to a second scale level of the plurality of scale levels; making a first determination, from the first result images, whether the first scale level is normal or abnormal; making a second determination, from the second result images, whether the second scale level is normal or abnormal; and determining that no error occurred in the test in response to both the first scale level and the second scale level being determined to be normal; or determining that an error occurred in the test in response to at least one scale level being determined to be abnormal.

    INTEGRATED CIRCUIT INCLUDING MULTIPLE HEIGHT CELL AND METHOD OF DESIGNING THE SAME
    9.
    发明申请
    INTEGRATED CIRCUIT INCLUDING MULTIPLE HEIGHT CELL AND METHOD OF DESIGNING THE SAME 有权

    公开(公告)号：US20220005801A1

    公开(公告)日：2022-01-06

    申请号：US17181672

    申请日：2021-02-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SungOk LEE ,  Sangdo PARK ,  Dayeon CHO

    IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238

    Abstract: An integrated circuit includes a standard cell continuously arranged on a first row and on a second row, the first row and second row extending parallel with each other in a first direction, the first row and the second row adjacent to each other in a second direction crossing the first direction, a first cell separator contacting a first row boundary of the standard cell on the first row and extending in the second direction, and a second cell separator contacting a second row boundary of the standard cell on the second row and extending in the second direction. The first cell separator and the second cell separator are discontinuous on a first row to second row boundary of the first row and the second row.

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