公开(公告)号：US20240386946A1

公开(公告)日：2024-11-21

申请号：US18539411

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjun Kim ,  Kyeongrim Baek ,  Seongook Jung ,  Sekeon Kim ,  Keonhee Cho

IPC: G11C11/418 ,  G11C5/06 ,  G11C11/419

Abstract: An embedded memory device includes a plurality of first bit cells configured to store data and connected between a first bitline and a first complementary bitline, and at least one first cropping cell connected between the first bitline and the first complementary bitline. The at least one first cropping cell electrically connects a global bitline to the first bitline and electrically connects a complementary global bitline to the first complementary bitline in response to a first crop wordline signal. The global bitline and the complementary global bitline are implemented as an upper metal member, and the first bitline and the first complementary bitline are implemented as a lower metal member disposed below the upper metal member.

公开(公告)号：US20240233812A1

公开(公告)日：2024-07-11

申请号：US18227355

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjun KIM ,  Sekeon Kim ,  Seongook Jung ,  Kyeongrim Baek ,  Keonhee Cho

IPC: G11C11/4096 ,  G11C5/06 ,  G11C11/4074

CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C11/4074

Abstract: A memory cell array of an SRAM including: a top memory cell array including top memory cells; and a bottom memory cell array including bottom memory cells, the top memory cells include: a first top memory cell between a power supply voltage and a middle node, and connected to a first top wordline, a first top bitline and a first top complementary bitline, the bottom memory cells include: a first bottom memory cell to operate with the first top memory cell, connected between the middle node and a ground voltage, and connected to a first bottom wordline, a first bottom bitline and a first bottom complementary bitline, and when write and read operations are not performed on the first top and bottom memory cells, the first top bitline, the first top complementary bitline, the first bottom bitline and the first bottom complementary bitline are connected to the middle node.