公开(公告)号：US11636894B2

公开(公告)日：2023-04-25

申请号：US17335509

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heekyung Choi ,  Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/419 ,  G11C11/4096 ,  G11C11/408 ,  G11C5/06 ,  G11C11/4099 ,  G11C11/4094

Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.

公开(公告)号：US20220115060A1

公开(公告)日：2022-04-14

申请号：US17478629

申请日：2021-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Taehyun Kim ,  Seongook Jung

IPC: G11C11/419 ,  G11C11/418

Abstract: A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

公开(公告)号：US20240386946A1

公开(公告)日：2024-11-21

申请号：US18539411

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjun Kim ,  Kyeongrim Baek ,  Seongook Jung ,  Sekeon Kim ,  Keonhee Cho

IPC: G11C11/418 ,  G11C5/06 ,  G11C11/419

Abstract: An embedded memory device includes a plurality of first bit cells configured to store data and connected between a first bitline and a first complementary bitline, and at least one first cropping cell connected between the first bitline and the first complementary bitline. The at least one first cropping cell electrically connects a global bitline to the first bitline and electrically connects a complementary global bitline to the first complementary bitline in response to a first crop wordline signal. The global bitline and the complementary global bitline are implemented as an upper metal member, and the first bitline and the first complementary bitline are implemented as a lower metal member disposed below the upper metal member.

公开(公告)号：US20240282367A1

公开(公告)日：2024-08-22

申请号：US18639330

申请日：2024-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Taehyun Kim ,  Seongook Jung

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

公开(公告)号：US20220130453A1

公开(公告)日：2022-04-28

申请号：US17332004

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.

公开(公告)号：US11990179B2

公开(公告)日：2024-05-21

申请号：US17478629

申请日：2021-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Taehyun Kim ,  Seongook Jung

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

公开(公告)号：US11568924B2

公开(公告)日：2023-01-31

申请号：US17332004

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.

公开(公告)号：US11356098B2

公开(公告)日：2022-06-07

申请号：US17353917

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo Moon ,  Jiyoung Kim ,  Seongook Jung ,  Jongsoo Lee

IPC: G11C7/10 ,  H03K19/173 ,  H03K19/0175 ,  G11C7/22 ,  H03K19/17788 ,  G11C7/14 ,  H03K19/017

Abstract: A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

公开(公告)号：US20220148644A1

公开(公告)日：2022-05-12

申请号：US17335509

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heekyung Choi ,  Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C5/06

Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.

公开(公告)号：US12231528B2

公开(公告)日：2025-02-18

申请号：US18197079

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo Moon ,  Jeonghyeok You ,  Seongook Jung ,  Taeryeong Kim ,  Hohyun Chae

IPC: H04L7/00 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14 ,  H03K5/00 ,  H03K19/20

Abstract: An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.