公开(公告)号：US12218669B2

公开(公告)日：2025-02-04

申请号：US18330731

申请日：2023-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-Ook Jung ,  Se Keon Kim ,  Hyunjun Kim ,  Kyeong Rim Baek ,  Keonhee Cho

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037

Abstract: A flip-flop includes an input logic circuit, a first latch, a second latch, and an output multiplexer; where the input logic circuit outputs a clock bar signal based on an input data bit and a clock signal, where the first latch and the second latch operate based on the input data bit, the clock signal, and a clock bar signal, where the output multiplexer operates based on outputs from nodes of the first and second nodes and outputs an output data bit, and where the input logic circuit has a uniform value in a period where there is no change of a value of the output data bit.

公开(公告)号：US11636894B2

公开(公告)日：2023-04-25

申请号：US17335509

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heekyung Choi ,  Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/419 ,  G11C11/4096 ,  G11C11/408 ,  G11C5/06 ,  G11C11/4099 ,  G11C11/4094

Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.

公开(公告)号：US20240386946A1

公开(公告)日：2024-11-21

申请号：US18539411

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjun Kim ,  Kyeongrim Baek ,  Seongook Jung ,  Sekeon Kim ,  Keonhee Cho

IPC: G11C11/418 ,  G11C5/06 ,  G11C11/419

Abstract: An embedded memory device includes a plurality of first bit cells configured to store data and connected between a first bitline and a first complementary bitline, and at least one first cropping cell connected between the first bitline and the first complementary bitline. The at least one first cropping cell electrically connects a global bitline to the first bitline and electrically connects a complementary global bitline to the first complementary bitline in response to a first crop wordline signal. The global bitline and the complementary global bitline are implemented as an upper metal member, and the first bitline and the first complementary bitline are implemented as a lower metal member disposed below the upper metal member.

公开(公告)号：US20220130453A1

公开(公告)日：2022-04-28

申请号：US17332004

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.

公开(公告)号：US11568924B2

公开(公告)日：2023-01-31

申请号：US17332004

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.

公开(公告)号：US20220148644A1

公开(公告)日：2022-05-12

申请号：US17335509

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heekyung Choi ,  Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C5/06

Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.

公开(公告)号：US20240233812A1

公开(公告)日：2024-07-11

申请号：US18227355

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjun KIM ,  Sekeon Kim ,  Seongook Jung ,  Kyeongrim Baek ,  Keonhee Cho

IPC: G11C11/4096 ,  G11C5/06 ,  G11C11/4074

CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C11/4074

Abstract: A memory cell array of an SRAM including: a top memory cell array including top memory cells; and a bottom memory cell array including bottom memory cells, the top memory cells include: a first top memory cell between a power supply voltage and a middle node, and connected to a first top wordline, a first top bitline and a first top complementary bitline, the bottom memory cells include: a first bottom memory cell to operate with the first top memory cell, connected between the middle node and a ground voltage, and connected to a first bottom wordline, a first bottom bitline and a first bottom complementary bitline, and when write and read operations are not performed on the first top and bottom memory cells, the first top bitline, the first top complementary bitline, the first bottom bitline and the first bottom complementary bitline are connected to the middle node.

公开(公告)号：US11670360B2

公开(公告)日：2023-06-06

申请号：US17335606

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C5/06

CPC classification number: G11C11/4085 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4099

Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first columns and including a plurality of word line assist cells in at least one second column; a plurality of word lines respectively extending on a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line assist cells; and a row driver configured to drive the plurality of word lines.

公开(公告)号：US20220139442A1

公开(公告)日：2022-05-05

申请号：US17335606

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4099 ,  G11C5/06

Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first columns and including a plurality of word line assist cells in at least one second column; a plurality of word lines respectively extending on a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line assist cells; and a row driver configured to drive the plurality of word lines.