公开(公告)号：US20220408001A1

公开(公告)日：2022-12-22

申请号：US17669731

申请日：2022-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo HWANG ,  Homin KANG ,  Jaeuk AHN ,  Serhoon LEE

IPC: H04N5/232 ,  G06F9/48

Abstract: An image signal processor includes a command queue circuit, an image processing engine and an interrupt control circuit. The command queue circuit stores a plurality of commands and sequentially provides the plurality of commands one by one. Each command of the plurality of commands includes an interrupt control value corresponding to each image unit of a plurality of image units. The plurality of commands are received from a control processor. The image processing engine receives the plurality of image units and sequentially processes the plurality of image units based on the plurality of commands sequentially provided from the command queue circuit. The interrupt control circuit receives the interrupt control value from the command queue circuit, determines one or more output interrupt event signals among a plurality of interrupt event signals based on the interrupt control value and generates an interrupt signal based on the output interrupt event signals.

公开(公告)号：US20210383498A1

公开(公告)日：2021-12-09

申请号：US17136494

申请日：2020-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilhyung CHA ,  Jinsoo PARK ,  Dongwoo LEE ,  Serhoon LEE ,  Sungjin HUH

IPC: G06T1/20 ,  G06T1/60 ,  G06F13/16 ,  G06F13/42 ,  G06F9/54

Abstract: An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.