公开(公告)号：US20210383498A1

公开(公告)日：2021-12-09

申请号：US17136494

申请日：2020-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilhyung CHA ,  Jinsoo PARK ,  Dongwoo LEE ,  Serhoon LEE ,  Sungjin HUH

IPC: G06T1/20 ,  G06T1/60 ,  G06F13/16 ,  G06F13/42 ,  G06F9/54

Abstract: An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.

公开(公告)号：US20200221409A1

公开(公告)日：2020-07-09

申请号：US16733650

申请日：2020-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinsoo PARK ,  Hyunpyo LEE ,  Byoungkon PARK ,  Jaeyoon LEE ,  Seungpyo HAN

IPC: H04W56/00

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The disclosure is A first apparatus for estimating a delay time in a synchronization system is provided. The first apparatus includes a detector configured to detect a request signal generated by a second apparatus, and a generator configured to generate a response signal corresponding to the request signal and output the response signal. The request signal is received through a cable from the second apparatus and the response signal is transmitted to the second apparatus through the cable.

公开(公告)号：US20210223315A1

公开(公告)日：2021-07-22

申请号：US17206288

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Seok SHIN ,  Jinsoo PARK

IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

Abstract: A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.

公开(公告)号：US20210168754A1

公开(公告)日：2021-06-03

申请号：US16641619

申请日：2018-07-13

Applicant: Samsung Electronics Co., Ltd

Inventor： Jinsoo PARK ,  Hyunpyo LEE ,  Jaeyoon LEE

IPC: H04W64/00 ,  H04W72/04 ,  H04W56/00

Abstract: The present invention relates to a communication technique for convergence of IoT technology and a 5G communication system for supporting a higher data transfer rate beyond a 4G system, and a system therefor. Also, the present invention provides a method for determining a location of a base station, the method comprising the steps of: receiving, from a terminal, a first message including location information of the terminal; and determining location information of the base station on the basis of the received location information of the terminal.

公开(公告)号：US20200225284A1

公开(公告)日：2020-07-16

申请号：US16544160

申请日：2019-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Seok SHIN ,  Jinsoo PARK

IPC: G01R31/3177 ,  G01R31/317

Abstract: A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.