公开(公告)号：US20210383498A1

公开(公告)日：2021-12-09

申请号：US17136494

申请日：2020-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilhyung CHA ,  Jinsoo PARK ,  Dongwoo LEE ,  Serhoon LEE ,  Sungjin HUH

IPC: G06T1/20 ,  G06T1/60 ,  G06F13/16 ,  G06F13/42 ,  G06F9/54

Abstract: An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.

公开(公告)号：US20230088614A1

公开(公告)日：2023-03-23

申请号：US18059607

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilhyung CHA ,  Jinsoo Park ,  Dongwoo Lee ,  Serhoon Lee ,  Sungjin Huh

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F13/42 ,  G06F13/16

Abstract: An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.