公开(公告)号：US20220384450A1

公开(公告)日：2022-12-01

申请号：US17734436

申请日：2022-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suncheul KIM ,  Youngsang LEE ,  Yunchul SHIN ,  Donghoon HAN

IPC: H01L27/108

Abstract: An integrated circuit device includes a substrate including an active region defined by a device isolation layer, the substrate defining a gate trench extending across the active region, a gate dielectric layer conformally covering an inner surface of the gate trench, and a gate electrode filling the gate trench on the gate dielectric layer. The gate electrode is composed of crystal grains of a single metal, and a diagonal length of at least one of the crystal grains is greater than a height of the active region that is in contact with the gate electrode.

公开(公告)号：US20240292598A1

公开(公告)日：2024-08-29

申请号：US18530748

申请日：2023-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suncheul KIM ,  Taeyeon KWON ,  Younjae CHO ,  Jihoon KIM ,  Hongsung MOON

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor memory device may include active regions defined on a substrate by a device isolation layer, each of the active regions including a first impurity region and a second impurity region, word lines on the active regions and extended in a first direction, capping insulating patterns covering top surfaces of the word lines, respectively, bit lines on the word lines and extended in a second direction crossing the first direction, contact plugs between the bit lines and connected to the second impurity region, and data storages on the contact plugs, respectively. Each of the word lines may include a first metal nitride layer and a second metal nitride layer on the first metal nitride layer. A resistivity of the second metal nitride layer may be smaller than a resistivity of the first metal nitride layer.

公开(公告)号：US20240098986A1

公开(公告)日：2024-03-21

申请号：US18524794

申请日：2023-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suncheul KIM ,  Donghyun LEE ,  Uihyoung LEE

IPC: H10B12/00

CPC classification number: H10B12/485

Abstract: A contact forming method may include providing a semiconductor substrate including a silicon oxide film to an interior of a chamber, subjecting a surface of the silicon oxide film to plasma nitrification treatment, supplying a source gas including TiCl4 and H2 onto the silicon oxide film subjected to the plasma nitrification treatment, and forming a barrier layer by igniting a plasma using the source gas.

公开(公告)号：US20220415902A1

公开(公告)日：2022-12-29

申请号：US17568117

申请日：2022-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suncheul KIM ,  Donghyun LEE ,  Uihyoung LEE

IPC: H01L27/108

Abstract: A contact forming method may include providing a semiconductor substrate including a silicon oxide film to an interior of a chamber, subjecting a surface of the silicon oxide film to plasma nitrification treatment, supplying a source gas including TiCl4 and H2 onto the silicon oxide film subjected to the plasma nitrification treatment, and forming a barrier layer by igniting a plasma using the source gas.