公开(公告)号：US09419011B2

公开(公告)日：2016-08-16

申请号：US14588506

申请日：2015-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunyeong Lee ,  Kyoung-Hoon Kim ,  Jin-Woo Park ,  SeungWoo Paek ,  Seok-won Lee ,  Taekeun Cho

IPC: H01L27/00 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L2224/32145

Abstract: Three-dimensional (3D) semiconductor devices are provided. The 3D semiconductor device includes a plurality of dummy pillars penetrating each cell pad of an electrode structure and the electrode structure disposed under each cell pad. Insulating patterns of a mold stack structure for formation of the electrode structure may be supported by the plurality of dummy pillars, so transformation and contact of the insulating patterns may be minimized or prevented.

Abstract translation: 提供三维（3D）半导体器件。 3D半导体器件包括穿过电极结构的每个电池衬垫的多个虚拟柱和设置在每个电池衬垫下方的电极结构。 用于形成电极结构的模具堆叠结构的绝缘图案可以由多个虚拟支柱支撑，因此可以最小化或防止绝缘图案的变形和接触。

公开(公告)号：US10546869B2

公开(公告)日：2020-01-28

申请号：US15800545

申请日：2017-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekeun Cho ,  Hongsoo Kim ,  Jong-Kook Park ,  TaeHee Lee

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11524 ,  H01L23/522 ,  H01L27/11578 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor device comprises a plurality of stack structures that include gate electrodes sequentially stacked on a substrate and are disposed along a first direction, and a plurality of separating insulation layers each of which is disposed between the stack structures. A plurality of vertical pillars penetrate each of the stack structures and are connected to the substrate. A plurality of bit lines are disposed on the vertical pillars and run across the stack structures in the first direction. A plurality of bit line contact structures connect the vertical pillars to the bit lines. A plurality of first cell dummy lines are disposed on the plurality of separating insulation layers and extend in a second direction crossing the first direction.

公开(公告)号：US20180261616A1

公开(公告)日：2018-09-13

申请号：US15800545

申请日：2017-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekeun Cho ,  Hongsoo Kim ,  Jong-Kook Park ,  TaeHee Lee

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11578 ,  H01L23/522

CPC classification number: H01L27/11573 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device comprises a plurality of stack structures that include gate electrodes sequentially stacked on a substrate and are disposed along a first direction, and a plurality of separating insulation layers each of which is disposed between the stack structures. A plurality of vertical pillars penetrate each of the stack structures and are connected to the substrate. A plurality of bit lines are disposed on the vertical pillars and run across the stack structures in the first direction. A plurality of bit line contact structures connect the vertical pillars to the bit lines. A plurality of first cell dummy lines are disposed on the plurality of separating insulation layers and extend in a second direction crossing the first direction.