Semiconductor device capable of adjusting memory page size based on a row address, a bank address and a power supply voltage
    1.
    发明授权
    Semiconductor device capable of adjusting memory page size based on a row address, a bank address and a power supply voltage 有权
    能够基于行地址,存储体地址和电源电压来调整存储器页面大小的半导体器件

    公开(公告)号:US08804455B2

    公开(公告)日:2014-08-12

    申请号:US13828604

    申请日:2013-03-14

    CPC classification number: G11C8/10 G11C5/00 G11C5/02 G11C8/06 G11C8/12

    Abstract: A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.

    Abstract translation: 半导体器件包括包括多个存储体的存储单元阵列和页面大小控制器。 页面尺寸控制器解码存储体选择地址或电源电压的一部分以及存储体选择地址的剩余部分,以使得多个存储体中的一个存储体使能或使多个存储体中的两个可以设置半导体的页面大小 设备。

    SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING MEMORY PAGE SIZE BASED ON A ROW ADDRESS AND A BANK ADDRESS
    2.
    发明申请
    SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING MEMORY PAGE SIZE BASED ON A ROW ADDRESS AND A BANK ADDRESS 有权
    可以根据地址和银行地址调整存储器页面大小的半导体器件

    公开(公告)号:US20130201778A1

    公开(公告)日:2013-08-08

    申请号:US13828604

    申请日:2013-03-14

    CPC classification number: G11C8/10 G11C5/00 G11C5/02 G11C8/06 G11C8/12

    Abstract: A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.

    Abstract translation: 半导体器件包括包括多个存储体的存储单元阵列和页面大小控制器。 页面尺寸控制器解码存储体选择地址或电源电压的一部分以及存储体选择地址的剩余部分,以使得多个存储体中的一个存储体使能或使多个存储体中的两个可以设置半导体的页面大小 设备。

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