中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.018 seconds)

    DELAY LOCKED LOOP INCLUDING A DELAY CODE GENERATOR
    2.
    发明申请
    DELAY LOCKED LOOP INCLUDING A DELAY CODE GENERATOR 审中-公开

    公开(公告)号：US20170338825A1

    公开(公告)日：2017-11-23

    申请号：US15599191

    申请日：2017-05-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoon Lee ,  Donghun Lee ,  Jaewon Lee

    IPC: H03L7/081 ,  H03L7/091 ,  H03K19/20

    CPC classification number: H03L7/0818 ,  H03K5/131 ,  H03K19/20 ,  H03K2005/00234 ,  H03L7/0816 ,  H03L7/085 ,  H03L7/091 ,  H03L7/10

    Abstract: A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

    Semiconductor device capable of adjusting memory page size based on a row address, a bank address and a power supply voltage
    4.
    发明授权
    Semiconductor device capable of adjusting memory page size based on a row address, a bank address and a power supply voltage 有权
    能够基于行地址，存储体地址和电源电压来调整存储器页面大小的半导体器件

    公开(公告)号：US08804455B2

    公开(公告)日：2014-08-12

    申请号：US13828604

    申请日：2013-03-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoon Lee ,  Uk Song Kang ,  Hoe Ju Chung

    IPC: G11C8/12

    CPC classification number: G11C8/10 ,  G11C5/00 ,  G11C5/02 ,  G11C8/06 ,  G11C8/12

    Abstract: A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.

    Abstract translation: 半导体器件包括包括多个存储体的存储单元阵列和页面大小控制器。 页面尺寸控制器解码存储体选择地址或电源电压的一部分以及存储体选择地址的剩余部分，以使得多个存储体中的一个存储体使能或使多个存储体中的两个可以设置半导体的页面大小 设备。

    Semiconductor memory device calibrating termination resistance and termination resistance calibration method thereof
    8.
    发明授权
    Semiconductor memory device calibrating termination resistance and termination resistance calibration method thereof 有权
    半导体存储器件校准端接电阻及其端接电阻校准方法

    公开(公告)号：US09118313B2

    公开(公告)日：2015-08-25

    申请号：US14466509

    申请日：2014-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoon Lee ,  Jin-Hee Park

    IPC: G11C11/00 ,  H03K19/00 ,  G11C7/12

    CPC classification number: H03K19/0005 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/12 ,  G11C2207/2254

    Abstract: Provided is a semiconductor memory device calibrating a termination resistance, the semiconductor memory device comprising self-adjustment logic configured to determine whether a value of an upper bit string of a calibration code generated in response to a calibration start signal is equal to or greater than an upper critical value of the calibration code, or is equal to or less than a lower critical value of the calibration code, and to generate an adjustment signal for adjusting a value of a termination resistance of a data output driver based on the determination result; and resistance calibration logic configured to provide the upper bit string to the self-adjustment logic, and to generate an updated calibration code by performing a calibration calculation based on the calibration code and a comparison signal generated according to a result of comparing a reference voltage and a voltage of a comparison target node.

    Abstract translation: 提供了校准端接电阻的半导体存储器件，所述半导体存储器件包括自调整逻辑，其被配置为确定响应于校准开始信号产生的校准代码的高位位串的值是否等于或大于 校准代码的上临界值或者等于或小于校准代码的较低临界值，并且基于确定结果生成用于调整数据输出驱动器的终端电阻的值的调整信号; 以及电阻校准逻辑，被配置为将所述高位串提供给所述自调节逻辑，并且通过基于所述校准代码执行校准计算以及根据比较参考电压和 比较目标节点的电压。

    SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING MEMORY PAGE SIZE BASED ON A ROW ADDRESS AND A BANK ADDRESS
    9.
    发明申请
    SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING MEMORY PAGE SIZE BASED ON A ROW ADDRESS AND A BANK ADDRESS 有权
    可以根据地址和银行地址调整存储器页面大小的半导体器件

    公开(公告)号：US20130201778A1

    公开(公告)日：2013-08-08

    申请号：US13828604

    申请日：2013-03-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoon Lee ,  Uk Song Kang ,  Hoe Ju Chung

    IPC: G11C8/10 ,  G11C8/12

    CPC classification number: G11C8/10 ,  G11C5/00 ,  G11C5/02 ,  G11C8/06 ,  G11C8/12

    Abstract: A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.

    Abstract translation: 半导体器件包括包括多个存储体的存储单元阵列和页面大小控制器。 页面尺寸控制器解码存储体选择地址或电源电压的一部分以及存储体选择地址的剩余部分，以使得多个存储体中的一个存储体使能或使多个存储体中的两个可以设置半导体的页面大小 设备。

    Delay locked loop including a delay code generator
    10.
    发明授权
    Delay locked loop including a delay code generator 有权

    公开(公告)号：US10305494B2

    公开(公告)日：2019-05-28

    申请号：US15599191

    申请日：2017-05-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoon Lee ,  Donghun Lee ,  Jaewon Lee

    IPC: H03L7/06 ,  H03L7/081 ,  H03L7/091 ,  H03K19/20 ,  H03K5/131 ,  H03K5/00

    Abstract: A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

Patent Agency Ranking