Scheduler and scheduling method for reconfigurable architecture
    1.
    发明授权
    Scheduler and scheduling method for reconfigurable architecture 有权
    可重构架构的调度和调度方法

    公开(公告)号:US09311270B2

    公开(公告)日:2016-04-12

    申请号:US14197591

    申请日:2014-03-05

    CPC classification number: G06F15/7885 G06F9/4881

    Abstract: A scheduler and scheduling method perform scheduling for a reconfigurable architecture. The scheduling, performed by the scheduler, includes path information extracting including extracting direct path information and indirect path information between functional units in a reconfigurable array complying with predefined architecture requirements, based on architecture information of the reconfigurable array, command selecting including selecting a command from a data flow graph (DFG) showing commands to be executed by the reconfigurable array, and scheduling including scheduling the selected command based on the extracted direct path information and indirect path information.

    Abstract translation: 调度器和调度方法对可重构架构执行调度。 由调度器执行的调度包括路径信息提取,包括基于可重配置阵列的体系结构信息,在可重配置阵列的可重构阵列中的功能单元之间提取直接路径信息和间接路径信息,命令选择包括从 显示由可重配置阵列执行的命令的数据流图(DFG),以及包括基于所提取的直接路径信息和间接路径信息来调度所选择的命令的调度。

    Reconfigurable processor and method for optimizing configuration memory
    9.
    发明授权
    Reconfigurable processor and method for optimizing configuration memory 有权
    可配置的处理器和优化配置存储器的方法

    公开(公告)号:US09535833B2

    公开(公告)日:2017-01-03

    申请号:US14461794

    申请日:2014-08-18

    CPC classification number: G06F12/0653 G06F9/30 G06F9/44505 H03M7/30

    Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

    Abstract translation: 提供了一种用于优化可重配置处理器的配置存储器的方法和装置。 优化可重配置处理器的配置存储器的方法包括基于可重构处理器的架构和关于配置存储器的信息来分析程序代码的循环的并行性,在每个周期中激活功能单元(FU)的调度组 基于分析的并行度生成循环,生成每个周期的配置数据,以及确定存储器映射以将生成的配置数据存储在配置存储器中。

Patent Agency Ranking