公开(公告)号：US20190158109A1

公开(公告)日：2019-05-23

申请号：US16191367

申请日：2018-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil KAVALA ,  Seon-kyoo LEE ,  Byung-hoon JEONG ,  Jeong-don IHM ,  Young-don CHOI

IPC: H03M1/78 ,  G11C5/14 ,  G05F3/08

CPC classification number: H03M1/785 ,  G05F3/08 ,  G11C5/147 ,  G11C7/14

Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

公开(公告)号：US20190096447A1

公开(公告)日：2019-03-28

申请号：US15975266

申请日：2018-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG-SU JANG ,  Man-jae YANG ,  Jeong-don IHM ,  Go-eun JUNG ,  Byung-hoon JEONG ,  Young-don CHOI

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C7/106 ,  G11C5/066 ,  G11C7/1033 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096 ,  G11C16/26 ,  G11C2207/107

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.