公开(公告)号：US20220077152A1

公开(公告)日：2022-03-10

申请号：US17199740

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Youngsin Kim ,  Kijin Park ,  Hoju Song ,  Dongkwan Yang ,  Sangho Yun ,  Gyuhyun Lee ,  Jieun Lee ,  Seunguk Han ,  Yoongi Hong

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.

公开(公告)号：US11690213B2

公开(公告)日：2023-06-27

申请号：US17199740

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Youngsin Kim ,  Kijin Park ,  Hoju Song ,  Dongkwan Yang ,  Sangho Yun ,  Gyuhyun Lee ,  Jieun Lee ,  Seunguk Han ,  Yoongi Hong

IPC: H10B12/00 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

CPC classification number: H10B12/315 ,  H01L29/4941 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7833

Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.

公开(公告)号：US20230328956A1

公开(公告)日：2023-10-12

申请号：US17936960

申请日：2022-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Son ,  Hojoong Kim ,  Youngsin Kim ,  Hyo-Seok Kim ,  Bongsik Choi ,  Taewoong Koo ,  Taeha Suh

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10897

Abstract: A semiconductor device includes a substrate including a first active pattern having first and second source/drain regions of a cell region, a device isolation layer in a trench defining the first active pattern on the cell region, a buffer layer on the cell region, a line structure extends in a third direction, extends from the cell region to a boundary region, and including a first conductive pattern that passes through the buffer layer and contacts the first source/drain region, a bit line on the first conductive pattern, and a first barrier pattern between the bit line and the first conductive pattern, a pair of spacers respectively on both sidewalls of the line structure, a contact on the second source/drain region, a landing pad on the contact, a first abrasive particle between the contact and the landing pad, and a data storage element on the landing pad.