公开(公告)号：US20220077152A1

公开(公告)日：2022-03-10

申请号：US17199740

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Youngsin Kim ,  Kijin Park ,  Hoju Song ,  Dongkwan Yang ,  Sangho Yun ,  Gyuhyun Lee ,  Jieun Lee ,  Seunguk Han ,  Yoongi Hong

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.

公开(公告)号：US11690213B2

公开(公告)日：2023-06-27

申请号：US17199740

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Youngsin Kim ,  Kijin Park ,  Hoju Song ,  Dongkwan Yang ,  Sangho Yun ,  Gyuhyun Lee ,  Jieun Lee ,  Seunguk Han ,  Yoongi Hong

IPC: H10B12/00 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

CPC classification number: H10B12/315 ,  H01L29/4941 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7833

Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.

公开(公告)号：US20250008722A1

公开(公告)日：2025-01-02

申请号：US18631884

申请日：2024-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeyoung KIM ,  Sangho Yun ,  Jeonghee Choi ,  Woojin Jung

IPC: H10B12/00 ,  H01L21/308 ,  H01L21/762

Abstract: A method of forming a pattern is provided. The method includes: forming a first recess in a substrate; forming a first mask layer on the substrate that extends into the first recess; performing a heat treatment process on the first mask layer; removing an upper portion of the first mask layer to form a first mask in the first recess, the first mask comprising a lower portion of the first mask layer; forming a second mask on the substrate and the first mask, the second mask comprising a material having a tolerance with respect to an etching process that is greater than that of the first mask; and performing an etching process on the substrate using the second mask as an etching mask to form the pattern on the substrate.

公开(公告)号：US11733601B2

公开(公告)日：2023-08-22

申请号：US17308484

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soonmok Ha ,  Jaehee Kim ,  Sangho Yun ,  Chan Hwang

IPC: G03F1/24

CPC classification number: G03F1/24

Abstract: An EUV photomask having a main area and a scribe lane area and reflecting EUV light includes a reflective multilayer film and an absorption pattern, wherein the scribe lane area includes first and second lanes, wherein the first lane includes first and second sub-lanes extending in the same direction as an extending direction of the first lane, wherein the first sub-lane includes a first dummy pattern that is a portion of the absorption pattern, and the second sub-lane includes a second dummy pattern that is a portion of the absorption pattern, and when EUV light that is not absorbed by the first and second dummy patterns and is reflected by the reflective multilayer film is irradiated at least twice by overlapping a negative tone photoresist, an amount of light exceeds a threshold dose of light in the negative tone photoresist corresponding to the first lane.

公开(公告)号：US20240112915A1

公开(公告)日：2024-04-04

申请号：US18474849

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janghoon Kim ,  Sangho Yun ,  Chan Hwang

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0274 ,  H01L21/31144

Abstract: A method of fabricating a semiconductor device may implement a desired mask pattern even without additionally performing an exposure process on any one of different regions of a substrate by forming a plurality of line patterns disposed at different intervals on the different regions, respectively, and applying a double patterning process to the plurality of line patterns. Such a method may increase product reliability and manufacturing economic feasibility of a semiconductor device.