公开(公告)号：US11647627B2

公开(公告)日：2023-05-09

申请号：US17168952

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Sangho Lee ,  Seoryong Park ,  Jiyoung Ahn ,  Kiseok Lee ,  Kiseok Lee ,  Yoonyoung Choi ,  Seunguk Han

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

公开(公告)号：US20210391259A1

公开(公告)日：2021-12-16

申请号：US17129083

申请日：2020-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung Ahn ,  Seunguk Han ,  Sunghwan Kim ,  Seoryong Park ,  Kiseok Lee ,  Yoonyoung Choi ,  Taehee Han ,  Jiseok Hong

IPC: H01L23/528

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

公开(公告)号：US20230232616A1

公开(公告)日：2023-07-20

申请号：US18186593

申请日：2023-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok HONG ,  Sangho Lee ,  Seoryong Park ,  Jiyoung Ahn ,  Kiseok Lee ,  Kiseok Lee ,  Yoonyoung Choi ,  Seunguk Han

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

公开(公告)号：US11557596B2

公开(公告)日：2023-01-17

申请号：US17192086

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seoryong Park ,  Seunguk Han ,  Jiyoung Ahn ,  Kiseok Lee ,  Yoonyoung Choi ,  Jiseok Hong

IPC: H01L27/11551 ,  H01L27/11519 ,  G11C8/14 ,  H01L27/11578 ,  G11C7/18 ,  H01L27/11565

Abstract: A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.

公开(公告)号：US20230411157A1

公开(公告)日：2023-12-21

申请号：US18136407

申请日：2023-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungkyo Lee ,  Jongin Kang ,  Gyeyoung Kim ,  Youngwoo Kim ,  Yonghan Park ,  Woojin Jung ,  Seunguk Han ,  Juyoung Huh

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L23/16 ,  H01L23/544

CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/0228 ,  H01L23/16 ,  H01L23/544

Abstract: A method of manufacturing a semiconductor device includes: forming a mask layer, a first separation layer, a first mandrel layer, a second separation layer and a second mandrel layer on a substrate; patterning the second mandrel layer to form second mandrel patterns; forming first spacers on the second mandrel patterns; removing the second mandrel patterns; patterning the second separation layer and the first mandrel layer to form first structures; forming a second spacer layer on the first structures and the first separation layer; anisotropically etching the second spacer layer to form second spacers on the first structures, and to form first dummy patterns and align key patterns on the first structures; and spin-coating a spin-on hard mask layer on the first separation layer, wherein the spin-on hard mask layer covers the first structures, the first dummy patterns and the align key patterns.

公开(公告)号：US11690213B2

公开(公告)日：2023-06-27

申请号：US17199740

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Youngsin Kim ,  Kijin Park ,  Hoju Song ,  Dongkwan Yang ,  Sangho Yun ,  Gyuhyun Lee ,  Jieun Lee ,  Seunguk Han ,  Yoongi Hong

IPC: H10B12/00 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

CPC classification number: H10B12/315 ,  H01L29/4941 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7833

Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.

公开(公告)号：US20210398569A1

公开(公告)日：2021-12-23

申请号：US17168952

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Sangho Lee ,  Seoryong Park ,  Jiyoung Ahn ,  Kiseok Lee ,  Kiseok Lee ,  Yoonyoung Choi ,  Seunguk Han

IPC: G11C5/06 ,  H01L27/108

Abstract: An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

公开(公告)号：US11908797B2

公开(公告)日：2024-02-20

申请号：US17129083

申请日：2020-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung Ahn ,  Seunguk Han ,  Sunghwan Kim ,  Seoryong Park ,  Kiseok Lee ,  Yoonyoung Choi ,  Taehee Han ,  Jiseok Hong

IPC: H01L23/528 ,  H01L29/06 ,  H10B12/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L23/5283 ,  H01L21/764 ,  H01L21/7682 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L23/5222 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

公开(公告)号：US20220077152A1

公开(公告)日：2022-03-10

申请号：US17199740

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Youngsin Kim ,  Kijin Park ,  Hoju Song ,  Dongkwan Yang ,  Sangho Yun ,  Gyuhyun Lee ,  Jieun Lee ,  Seunguk Han ,  Yoongi Hong

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.

公开(公告)号：US08901646B2

公开(公告)日：2014-12-02

申请号：US13727995

申请日：2012-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namho Jeon ,  Min-chul Park ,  Seunguk Han

IPC: H01L29/66 ,  G11C11/408 ,  H01L27/108 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L27/088 ,  G11C11/4085 ,  G11C11/4087 ,  H01L27/0207 ,  H01L27/10897

Abstract: A semiconductor device may include a substrate including an active region defined by a device isolation layer, gate electrodes extending in a first direction on the substrate and spaced apart from each other, gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other, and a first contact plug disposed on the active region under a space confined by the adjacent gate electrodes and adjacent gate tabs. The space may include a first region having a first width and a second region having a second width smaller than the first width, the first contact plug may be disposed on the active region under the second region.

Abstract translation: 半导体器件可以包括：衬底，其包括由器件隔离层限定的有源区，沿着第一方向在衬底上延伸并且彼此间隔开的栅电极，栅极突片沿与第一方向不同的第二方向延伸并连接相邻 栅极彼此间隔开，栅极突片彼此间隔开;以及第一接触插塞，其设置在由相邻的栅电极和相邻的栅极接线片限定的空间之下的有源区域上。 空间可以包括具有第一宽度的第一区域和具有小于第一宽度的第二宽度的第二区域，第一接触插塞可以设置在第二区域下方的有源区域上。