公开(公告)号：US20060063338A1

公开(公告)日：2006-03-23

申请号：US10946030

申请日：2004-09-20

申请人： Santosh Menon ,  Hemanshu Bhatt

发明人： Santosh Menon ,  Hemanshu Bhatt

IPC分类号： H01L21/336

CPC分类号： H01L21/26533 ,  H01L21/02118 ,  H01L21/02137 ,  H01L21/02164 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/76283 ,  H01L29/78609

摘要： The present invention is directed to structures and fabrication methods used to construct an improved shallow trench isolation structure are disclosed. The method involves providing a semiconductor substrate having a shallow isolation trench. The trench is implanted with oxygen to form an implanted region at the bottom of the trench. The trench is filled with dielectric materials. The substrate is planarized and then annealed to complete formation of the isolation structure. A structure having an improved isolation structure is also disclosed. The structure comprises a substrate configured to include a shallow trench that is filled with dielectric material. An insulating extension is formed by oxygen implantation of the regions underlying the shallow trench.

摘要翻译： 本发明涉及用于构造改进的浅沟槽隔离结构的结构和制造方法。 该方法包括提供具有浅隔离沟槽的半导体衬底。 沟槽被注入氧气以在沟槽的底部形成注入区域。 沟槽填充介电材料。 将基材平面化，然后退火以完成隔离结构的形成。 还公开了具有改进的隔离结构的结构。 该结构包括被配置为包括填充有电介质材料的浅沟槽的衬底。 通过浅沟槽下面的区域的氧注入形成绝缘延伸。

公开(公告)号：US20060088990A1

公开(公告)日：2006-04-27

申请号：US10971961

申请日：2004-10-22

申请人： Santosh Menon ,  Hemanshu Bhatt ,  David Pritchard

发明人： Santosh Menon ,  Hemanshu Bhatt ,  David Pritchard

IPC分类号： H01L21/44

CPC分类号： H01L21/76895

摘要： The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.

摘要翻译： 本发明涉及一种制造局部​​互连的方法。 所公开的方法包括在晶体管的两个电触点之上的ILD中形成两个分离的空腔。 第一腔向下延伸到下面的蚀刻停止层。 然后用保护层填充第一个空腔。 然后，第二腔形成在第一腔附近并向下延伸以露出下面的蚀刻停止层。 去除保护层以形成包括第一和第二空腔的扩展空腔，其暴露扩展空腔中的下面的蚀刻停止层。 扩散腔中的蚀刻停止材料也被去除以暴露下面的栅极接触并暴露源极或漏极接触中的一个。 然后将栅极触点与暴露的源极或漏极触点中的一个电连接以形成局部互连。

公开(公告)号：US20060279005A1

公开(公告)日：2006-12-14

申请号：US11506659

申请日：2006-08-18

申请人： Santosh Menon ,  Hemanshu Bhatt

发明人： Santosh Menon ,  Hemanshu Bhatt

IPC分类号： H01L21/20

CPC分类号： H01L23/5228 ,  H01L21/3215 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

摘要翻译： 在半导体器件的“金属层”中制造电子器件。 每个金属层包括支撑导电层的电介质层，其包括导电路径和电子器件。 金属层堆叠在彼此的顶部，使得电介质层分离相邻的导电层。 电子设备可以是诸如电阻器的无源器件。 电阻器通过将金属沉积到介电层上，然后用氧气注入金属而形成。 导电层可以由诸如铜和铝的材料形成。

公开(公告)号：US20060054997A1

公开(公告)日：2006-03-16

申请号：US10944373

申请日：2004-09-16

申请人： Santosh Menon ,  Hemanshu Bhatt

发明人： Santosh Menon ,  Hemanshu Bhatt

IPC分类号： H01L21/20 ,  H01L29/00

CPC分类号： H01L23/5228 ,  H01L21/3215 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

公开(公告)号：US07434198B2

公开(公告)日：2008-10-07

申请号：US11323401

申请日：2005-12-29

申请人： Nadya Strelkova ,  Santosh Menon

发明人： Nadya Strelkova ,  Santosh Menon

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is closer than a selected minimum distance from a polygon edge opposite the critical edge, constructing a critical region bounded by the critical edge and the polygon edge opposite the critical edge, comparing the critical region to a potential defect criterion, and generating as output a location of the critical region when the critical region satisfies the potential defect criterion.

摘要翻译： 从用于集成电路的校正的掩模设计中检测潜在故障的方法包括以下步骤：接收用于集成电路的校正的掩模设计作为输入，搜索校正的掩模设计以找到比所选择的最小值更接近的多边形的临界边缘 距离与边缘相对的多边形边缘的距离，构建由临界边界和与临界边缘相反的多边形边界限定的临界区域，将临界区域与潜在缺陷标准进行比较，以及当临界区域的位置 临界区域满足潜在的缺陷准则。

公开(公告)号：US20070157152A1

公开(公告)日：2007-07-05

申请号：US11323401

申请日：2005-12-29

申请人： Nadya Strelkova ,  Santosh Menon

发明人： Nadya Strelkova ,  Santosh Menon

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F1/36

摘要： A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is closer than a selected minimum distance from a polygon edge opposite the critical edge, constructing a critical region bounded by the critical edge and the polygon edge opposite the critical edge, comparing the critical region to a potential defect criterion, and generating as output a location of the critical region when the critical region satisfies the potential defect criterion.

摘要翻译： 从用于集成电路的校正的掩模设计中检测潜在故障的方法包括以下步骤：接收用于集成电路的校正的掩模设计作为输入，搜索校正的掩模设计以找到比所选择的最小值更接近的多边形的临界边缘 距离与边缘相对的多边形边缘的距离，构建由临界边界和与临界边缘相反的多边形边界限定的临界区域，将临界区域与潜在缺陷标准进行比较，以及当临界区域的位置 临界区域满足潜在的缺陷准则。