公开(公告)号：US07856581B1

公开(公告)日：2010-12-21

申请号：US11520530

申请日：2006-09-12

申请人： Sassan Tabatabaei ,  Yervant Zorian

发明人： Sassan Tabatabaei ,  Yervant Zorian

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318508

摘要： Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.

摘要翻译： 对于包括一些片上组件（例如，I-O，测试处理器，软封装等）的系统，提供参数测量单元（PMU）能力的外部测试单元以及执行的各种测试描述了各种方法和装置 在I-Os上通过片上测试逻辑，由外部测试单元提供的测试矢量模式。

公开(公告)号：US07844022B2

公开(公告)日：2010-11-30

申请号：US11590652

申请日：2006-10-31

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： H04L7/00

CPC分类号： G01R29/26 ,  G01R31/31709 ,  H04L1/205

摘要： The present subject matter is directed to methodologies for measuring jitter spectral content in a sampled signal using continuous time interval analyzers (CTIA) for characterization and test of clock signals and high-speed digital interfaces. The methodology takes advantage of anti-aliasing aspects of random sampling (RS) in a time interval error (TIE) based analysis methodology by randomizing timing of samples relative to signal edges and/or intervals between signal edges.

摘要翻译： 本主题涉及使用连续时间间隔分析器（CTIA）测量采样信号中的抖动频谱含量的方法，用于表征和测试时钟信号和高速数字接口。 该方法利用基于时间间隔误差（TIE）的分析方法中的随机抽样（RS）的抗锯齿方面，通过随机化样本相对于信号边缘的时序和/或信号边缘之间的间隔。

公开(公告)号：US07598726B1

公开(公告)日：2009-10-06

申请号：US11510035

申请日：2006-08-24

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318508

摘要： Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I/Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, a Device Interface Board (DIB) that includes resistors between the chip and the external tester, and various tests performed on the I/Os by the on-chip testing logic and external testing unit facilitated through the DIB.

摘要翻译： 对于包括一些芯片组件（例如I / O，测试处理器，软封装等）的系统，提供参数测量单元（PMU）能力的外部测试单元，设备接口板 （DIB），其包括芯片和外部测试仪之间的电阻，以及片上测试逻辑和外部测试单元通过DIB进行的对I / O执行的各种测试。

公开(公告)号：US07590902B1

公开(公告)日：2009-09-15

申请号：US11520423

申请日：2006-09-12

申请人： Sassan Tabatabaei ,  Yervant Zorian

发明人： Sassan Tabatabaei ,  Yervant Zorian

IPC分类号： G01R31/28

CPC分类号： G01R31/318572 ,  G01R31/318508

摘要： Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.

摘要翻译： 对于包括一些片上组件（例如，I-O，测试处理器，软封装等）的系统，提供参数测量单元（PMU）能力的外部测试单元以及执行的各种测试描述了各种方法和装置 在I-Os上通过片上测试逻辑，由外部测试单元提供的测试矢量模式。

公开(公告)号：US20090132207A1

公开(公告)日：2009-05-21

申请号：US12267107

申请日：2008-11-07

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G01R23/00

CPC分类号： G01R31/31709

摘要： Disclosed is a system and related methodology for providing fast low frequency jitter rejection in the measurement of signals under test. A signal under test may be sampled alternately with a reference signal under similar conditions. The resulting sampled signal blocks may then be processed to subtract the known calibrated value of the reference signal from the average signal under test.

摘要翻译： 公开了一种用于在测量被测信号时提供快速低频抖动抑制的系统和相关方法。 在类似条件下，可以用参考信号交替地对被测信号进行采样。 然后可以对所得到的采样信号块进行处理，以从所测试的平均信号中减去参考信号的已知校准值。

公开(公告)号：US20060161361A1

公开(公告)日：2006-07-20

申请号：US11301275

申请日：2005-12-08

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G06F19/00

CPC分类号： G01R31/31709 ,  H04L1/205

摘要： Methodologies are disclosed for analyzing periodic jitter is a signal pattern using a continuous time interval analyzer. Sampled signal patterns may be correlated using time interval error calculations to determine start and stop sequences within sampled blocks of signal data while sampling synchronization may be achieved based on time interval calculations or pattern interval error calculations.

公开(公告)号：US20060047450A1

公开(公告)日：2006-03-02

申请号：US10930683

申请日：2004-08-31

申请人： Sassan Tabatabaei ,  Mordechai Ben-Zeev ,  Paul Miller

发明人： Sassan Tabatabaei ,  Mordechai Ben-Zeev ,  Paul Miller

IPC分类号： G06F19/00

CPC分类号： G01R31/31709

摘要： Methods for estimating data-dependent jitter (DDJ) from measured samples of a transmitted data signal include a first exemplary step of obtaining a plurality of measurements (e.g., time tags and event counts for selected pulse widths in the data signal). Such measurements may be obtained at predetermined intervals within a transmitted signal or may be obtained at randomly selected intervals, and should yield measurements for each data pulse in a repeating data pattern. An average unit interval value representative of the average bit time of the transmitted signal is determined. Time interval error estimates representative of the timing deviation from each signal edge's measured value relative to its ideal value (determined in part from the calculated average unit interval value) are also determined, as well as a classification for each measured signal edge relative to a corresponding data pulse in the repeating data pattern. DDJ delta lines are then calculated for signal edges of each pulse width in the transmitted data pattern, from which peak-to-peak DDJ values and/or estimates of duty-cycle-distortion (DCD) can be determined.

摘要翻译： 用于从发送的数据信号的测量样本估计数据相关抖动（DDJ）的方法包括获得多个测量（例如，数据信号中所选择的脉冲宽度的时间标签和事件计数）的第一示例性步骤。 这样的测量可以以发送信号内的预定间隔获得，或者可以以随机选择的间隔获得，并且应该产生重复数据模式中每个数据脉冲的测量。 确定表示发送信号的平均位时间的平均单位间隔值。 时间间隔误差估计代表每个信号边缘的测量值相对于其理想值的时间偏差（由计算出的平均单位间隔值部分确定），以及相对于相应的每个测量信号边缘的分类 重复数据模式中的数据脉冲。 然后针对发送数据模式中的每个脉冲宽度的信号边缘计算DDJ delta线，从而可以确定峰 - 峰DDJ值和/或占空比失真（DCD）的估计。

公开(公告)号：US08255188B2

公开(公告)日：2012-08-28

申请号：US12267107

申请日：2008-11-07

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： H04B15/00

CPC分类号： G01R31/31709

摘要： Disclosed is a system and related methodology for providing fast low frequency jitter rejection in the measurement of signals under test. A signal under test may be sampled alternately with a reference signal under similar conditions. The resulting sampled signal blocks may then be processed to subtract the known calibrated value of the reference signal from the average signal under test.

摘要翻译： 公开了一种用于在测量被测信号时提供快速低频抖动抑制的系统和相关方法。 在类似条件下，可以用参考信号交替地对被测信号进行采样。 然后可以对所得到的采样信号块进行处理，以从所测试的平均信号中减去参考信号的已知校准值。

公开(公告)号：US08064293B2

公开(公告)日：2011-11-22

申请号：US12910158

申请日：2010-10-22

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G04F8/00 ,  G04F10/00

CPC分类号： G04F10/00 ,  G01R31/31922 ,  H03M1/14

摘要： The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

摘要翻译： 本主题针对高速高分辨率和精度时间插值电路。 内插器使用基本的双斜坡时间 - 数字转换器架构，但提供电路和方法来提高精度，减少有效的本征抖动并减少测量时间。 本主题的改进方面对应于引入电流镜以改善建立时间，用于改进分辨率的高频时钟和用于提高分辨率和精度的ADC采样处理。

公开(公告)号：US07843771B2

公开(公告)日：2010-11-30

申请号：US11956530

申请日：2007-12-14

申请人： Sassan Tabatabaei

发明人： Sassan Tabatabaei

IPC分类号： G04F8/00 ,  G04F10/00 ,  H03K5/22

CPC分类号： G04F10/00 ,  G01R31/31922 ,  H03M1/14

摘要： The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

摘要翻译： 本主题针对高速高分辨率和精度时间插值电路。 内插器使用基本的双斜坡时间 - 数字转换器架构，但提供电路和方法来提高精度，减少有效的本征抖动并减少测量时间。 本主题的改进方面对应于引入电流镜以改善建立时间，用于改进分辨率的高频时钟和用于提高分辨率和精度的ADC采样处理。