公开(公告)号：US08786341B1

公开(公告)日：2014-07-22

申请号：US13833360

申请日：2013-03-15

Applicant: Silicon Laboratories Inc.

Inventor： Colin Weltin-Wu ,  Yunteng Huang

IPC: H03L7/06

CPC classification number: H03L7/1972 ,  H03L7/10

Abstract: A digital frequency synthesizer provides absolute phase lock and shorter settling time through the use of a digital filter with a phase and frequency path. Control logic control disables the frequency path during the frequency acquisition and sets a wide bandwidth. After frequency acquisition, a counter with digital phase information is reset using the input clock signal to bring the output phase closer to lock with the input signal and the control logic enables the phase path in the digital loop filter to achieve phase lock with a narrower bandwidth than the initial bandwidth.

Abstract translation: 数字频率合成器通过使用具有相位和频率路径的数字滤波器提供绝对锁相和较短的建立时间。 控制逻辑控制在频率采集期间禁用频率路径，并设置宽带宽。 在频率采集之后，使用输入时钟信号复位具有数字相位信息的计数器，使输出相位更接近与输入信号锁定，并且控制逻辑使数字环路滤波器中的相位路径能够实现较窄带宽的锁相 比起初始带宽。

公开(公告)号：US20140176201A1

公开(公告)日：2014-06-26

申请号：US13724960

申请日：2012-12-21

Applicant: SILICON LABORATORIES INC.

Inventor： Colin Weltin-Wu ,  Yunteng Huang ,  Manu Seth

IPC: H03K5/13

CPC classification number: H03K5/131

Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.

Abstract translation: 分数N分频器提供分频时钟信号。 在具有与分数N分频器的数字量化误差成线性比例的延迟的数字 - 时间转换器电路中产生经调整的分频时钟信号。 调整后的分频时钟信号基于充电到预定电平的第一和第二电容器产生。 第一和第二电容器的充电在分频时钟的交替周期中交错。 用对应于各个数字量化误差的电流对每个电容器的充电与固定电流进行充电。 响应于第一电容器充电到预定电压而产生经调整的分频时钟信号的第一脉冲的第一边缘，并且响应于第二电容器充电而产生经调整的分频时钟信号的下一脉冲的第一边沿 预定电压。

公开(公告)号：US08860514B2

公开(公告)日：2014-10-14

申请号：US13724960

申请日：2012-12-21

Applicant: Silicon Laboratories Inc.

Inventor： Colin Weltin-Wu ,  Yunteng Huang ,  Manu Seth

IPC: H03K3/02 ,  H03B5/30 ,  H03B19/00 ,  H03L1/02 ,  H03K5/13

CPC classification number: H03K5/131

Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.

Abstract translation: 分数N分频器提供分频时钟信号。 在具有与分数N分频器的数字量化误差成线性比例的延迟的数字 - 时间转换器电路中产生经调整的分频时钟信号。 调整后的分频时钟信号基于充电到预定电平的第一和第二电容器产生。 第一和第二电容器的充电在分频时钟的交替周期中交错。 用对应于各个数字量化误差的电流对每个电容器的充电与固定电流进行充电。 响应于第一电容器充电到预定电压而产生经调整的分频时钟信号的第一脉冲的第一边缘，并且响应于第二电容器充电而产生经调整的分频时钟信号的下一脉冲的第一边沿 预定电压。