公开(公告)号：US09252707B2

公开(公告)日：2016-02-02

申请号：US13721642

申请日：2012-12-20

Applicant: Silicon Laboratories Inc.

Inventor： Manu Seth ,  Aaron Caffee

IPC: H03B5/36

CPC classification number: H03B5/362 ,  H03B5/366

Abstract: A technique for tracking changes in bias conditions of a microelectromechanical system (MEMS) device includes applying an electrode bias signal to an electrode of the MEMS device. The technique includes applying a mass bias signal to a mass of the MEMS device suspended from a substrate of the MEMS device. The technique includes generating the mass bias signal based on a target mass-to-electrode bias signal level and a signal level of the electrode bias signal.

Abstract translation: 用于跟踪微机电系统（MEMS）器件的偏置条件变化的技术包括将电极偏置信号施加到MEMS器件的电极。 该技术包括将质量偏置信号施加到从MEMS器件的衬底悬挂的MEMS器件的质量。 该技术包括基于目标质量对电极偏置信号电平和电极偏置信号的信号电平产生质量偏置信号。

公开(公告)号：US08860514B2

公开(公告)日：2014-10-14

申请号：US13724960

申请日：2012-12-21

Applicant: Silicon Laboratories Inc.

Inventor： Colin Weltin-Wu ,  Yunteng Huang ,  Manu Seth

IPC: H03K3/02 ,  H03B5/30 ,  H03B19/00 ,  H03L1/02 ,  H03K5/13

CPC classification number: H03K5/131

Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.

Abstract translation: 分数N分频器提供分频时钟信号。 在具有与分数N分频器的数字量化误差成线性比例的延迟的数字 - 时间转换器电路中产生经调整的分频时钟信号。 调整后的分频时钟信号基于充电到预定电平的第一和第二电容器产生。 第一和第二电容器的充电在分频时钟的交替周期中交错。 用对应于各个数字量化误差的电流对每个电容器的充电与固定电流进行充电。 响应于第一电容器充电到预定电压而产生经调整的分频时钟信号的第一脉冲的第一边缘，并且响应于第二电容器充电而产生经调整的分频时钟信号的下一脉冲的第一边沿 预定电压。

公开(公告)号：US08981860B2

公开(公告)日：2015-03-17

申请号：US13721630

申请日：2012-12-20

Applicant: Silicon Laboratories Inc.

Inventor： Aaron Caffee ,  Manu Seth ,  Brian Drost

IPC: H03L5/00 ,  H03B5/30 ,  B81B7/02

CPC classification number: H03B5/30 ,  B81B7/02 ,  H03B2200/001

Abstract: An apparatus includes a microelectromechanical system (MEMS) device configured as part of an oscillator. The MEMS device includes a mass suspended from a substrate of the MEMS, a first electrode configured to provide a first signal based on a displacement of the mass, and a second electrode configured to receive a second signal based on the first signal. The apparatus includes an amplifier coupled to the first electrode and a first node. The amplifier is configured to generate an output signal, the output signal being based on the first signal and a first gain. The apparatus includes an attenuator configured to attenuate the output signal based on a second gain and provide as the second signal an attenuated version of the output signal.

Abstract translation: 一种装置包括被配置为振荡器的一部分的微机电系统（MEMS）装置。 MEMS器件包括从MEMS的衬底悬挂的质量，第一电极，被配置为基于质量的位移提供第一信号，以及第二电极，被配置为基于第一信号接收第二信号。 该装置包括耦合到第一电极和第一节点的放大器。 放大器被配置为产生输出信号，输出信号基于第一信号和第一增益。 该装置包括衰减器，其被配置为基于第二增益来衰减输出信号，并将输出信号的衰减版本提供为第二信号。

公开(公告)号：US20140176248A1

公开(公告)日：2014-06-26

申请号：US13721630

申请日：2012-12-20

Applicant: Silicon Laboratories Inc.

Inventor： Aaron Caffee ,  Manu Seth ,  Brian Drost

IPC: H03B5/30 ,  B81B7/02

CPC classification number: H03B5/30 ,  B81B7/02 ,  H03B2200/001

Abstract: An apparatus includes a microelectromechanical system (MEMS) device configured as part of an oscillator. The MEMS device includes a mass suspended from a substrate of the MEMS, a first electrode configured to provide a first signal based on a displacement of the mass, and a second electrode configured to receive a second signal based on the first signal. The apparatus includes an amplifier coupled to the first electrode and a first node. The amplifier is configured to generate an output signal, the output signal being based on the first signal and a first gain. The apparatus includes an attenuator configured to attenuate the output signal based on a second gain and provide as the second signal an attenuated version of the output signal.

Abstract translation: 一种装置包括被配置为振荡器的一部分的微机电系统（MEMS）装置。 MEMS器件包括从MEMS的衬底悬挂的质量，第一电极，被配置为基于质量的位移提供第一信号，以及第二电极，被配置为基于第一信号接收第二信号。 该装置包括耦合到第一电极和第一节点的放大器。 放大器被配置为产生输出信号，输出信号基于第一信号和第一增益。 该装置包括衰减器，其被配置为基于第二增益来衰减输出信号，并将输出信号的衰减版本提供为第二信号。

公开(公告)号：US20140176201A1

公开(公告)日：2014-06-26

申请号：US13724960

申请日：2012-12-21

Applicant: SILICON LABORATORIES INC.

Inventor： Colin Weltin-Wu ,  Yunteng Huang ,  Manu Seth

IPC: H03K5/13

CPC classification number: H03K5/131

Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.

Abstract translation: 分数N分频器提供分频时钟信号。 在具有与分数N分频器的数字量化误差成线性比例的延迟的数字 - 时间转换器电路中产生经调整的分频时钟信号。 调整后的分频时钟信号基于充电到预定电平的第一和第二电容器产生。 第一和第二电容器的充电在分频时钟的交替周期中交错。 用对应于各个数字量化误差的电流对每个电容器的充电与固定电流进行充电。 响应于第一电容器充电到预定电压而产生经调整的分频时钟信号的第一脉冲的第一边缘，并且响应于第二电容器充电而产生经调整的分频时钟信号的下一脉冲的第一边沿 预定电压。

公开(公告)号：US20140176251A1

公开(公告)日：2014-06-26

申请号：US13721642

申请日：2012-12-20

Applicant: SILICON LABORATORIES INC.

Inventor： Manu Seth ,  Aaron Caffee

IPC: H03B28/00

CPC classification number: H03B5/362 ,  H03B5/366

Abstract: A technique for tracking changes in bias conditions of a microelectromechanical system (MEMS) device includes applying an electrode bias signal to an electrode of the MEMS device. The technique includes applying a mass bias signal to a mass of the MEMS device suspended from a substrate of the MEMS device. The technique includes generating the mass bias signal based on a target mass-to-electrode bias signal level and a signal level of the electrode bias signal.

Abstract translation: 用于跟踪微机电系统（MEMS）器件的偏置条件变化的技术包括将电极偏置信号施加到MEMS器件的电极。 该技术包括将质量偏置信号施加到从MEMS器件的衬底悬挂的MEMS器件的质量。 该技术包括基于目标质量对电极偏置信号电平和电极偏置信号的信号电平产生质量偏置信号。