公开(公告)号：US10141418B1

公开(公告)日：2018-11-27

申请号：US14830241

申请日：2015-08-19

申请人： Steven R. J. Brueck ,  Stephen D. Hersee ,  Seung-Chang Lee ,  Daniel Feezell

发明人： Steven R. J. Brueck ,  Stephen D. Hersee ,  Seung-Chang Lee ,  Daniel Feezell

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L29/16 ,  H01L29/04 ,  H01L21/02

摘要： A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

公开(公告)号：US09257535B2

公开(公告)日：2016-02-09

申请号：US14725719

申请日：2015-05-29

申请人： Seung-Chang Lee ,  Steven Brueck ,  Daniel Feezell

发明人： Seung-Chang Lee ,  Steven Brueck ,  Daniel Feezell

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/16 ,  H01L29/20 ,  H01L21/02 ,  B82Y10/00

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02241 ,  H01L21/02603 ,  H01L21/30612 ,  H01L21/30635 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7841 ,  H01L29/78696

摘要： A method and structure for a semiconductor transistor, including various embodiments. In embodiments, a transistor channel can be formed between a semiconductor source and a semiconductor drain, wherein a transistor gate oxide completely surrounds the transistor channel and a transistor gate metal that completely surrounds the transistor gate oxide. Related fabrication processes are presented for similar device embodiments based on a Group III-V semiconductor material and silicon-on-insulator materials.

公开(公告)号：US20150263134A1

公开(公告)日：2015-09-17

申请号：US14725719

申请日：2015-05-29

申请人： Seung-Chang Lee ,  Steven Brueck ,  Daniel Feezell

发明人： Seung-Chang Lee ,  Steven Brueck ,  Daniel Feezell

IPC分类号： H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02241 ,  H01L21/02603 ,  H01L21/30612 ,  H01L21/30635 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7841 ,  H01L29/78696

摘要： A method and structure for a semiconductor transistor, including various embodiments. In embodiments, a transistor channel can be formed between a semiconductor source and a semiconductor drain, wherein a transistor gate oxide completely surrounds the transistor channel and a transistor gate metal that completely surrounds the transistor gate oxide. Related fabrication processes are presented for similar device embodiments based on a Group III-V semiconductor material and silicon-on-insulator materials.

摘要翻译： 包括各种实施例的半导体晶体管的方法和结构。 在实施例中，可以在半导体源和半导体漏极之间形成晶体管沟道，其中晶体管栅极氧化物完全围绕晶体管沟道和完全围绕晶体管栅极氧化物的晶体管栅极金属。 针对基于III-V族半导体材料和绝缘体上硅材料的类似器件实施例提出了相关的制造工艺。

公开(公告)号：US09076813B1

公开(公告)日：2015-07-07

申请号：US14156176

申请日：2014-01-15

申请人： Seung-Chang Lee ,  Steven Brueck ,  Daniel Feezell

发明人： Seung-Chang Lee ,  Steven Brueck ,  Daniel Feezell

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  B82Y15/00

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02241 ,  H01L21/02603 ,  H01L21/30612 ,  H01L21/30635 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7841 ,  H01L29/78696

摘要： A method and structure for a semiconductor transistor, including various embodiments. In embodiments, a transistor channel can be formed between a semiconductor source and a semiconductor drain, wherein a transistor gate oxide completely surrounds the transistor channel and a transistor gate metal that completely surrounds the transistor gate oxide. Related fabrication processes are presented for similar device embodiments based on a Group III-V semiconductor material and silicon-on-insulator materials.

摘要翻译： 包括各种实施例的半导体晶体管的方法和结构。 在实施例中，可以在半导体源和半导体漏极之间形成晶体管沟道，其中晶体管栅极氧化物完全围绕晶体管沟道和完全围绕晶体管栅极氧化物的晶体管栅极金属。 针对基于III-V族半导体材料和绝缘体上硅材料的类似器件实施例提出了相关的制造工艺。

公开(公告)号：US20120007102A1

公开(公告)日：2012-01-12

申请号：US13179346

申请日：2011-07-08

申请人： Daniel Feezell ,  Rajat Sharma ,  Arpan Chakraborty ,  Troy Anthony Trottier ,  Thomas Katona ,  Mark D'Evelyn

发明人： Daniel Feezell ,  Rajat Sharma ,  Arpan Chakraborty ,  Troy Anthony Trottier ,  Thomas Katona ,  Mark D'Evelyn

IPC分类号： H01L33/02

CPC分类号： H01L27/156 ,  H01L33/14

摘要： A light emitting device comprising a gallium and nitrogen containing substrate. The device also has an electrically isolating material grown between the substrate and an active region such that the light emitting device is operable at a voltage greater than 10V.

摘要翻译： 一种包含含镓和氮的衬底的发光器件。 该器件还具有在衬底和有源区之间生长的电隔离材料，使得发光器件可工作在大于10V的电压。

公开(公告)号：US20070280320A1

公开(公告)日：2007-12-06

申请号：US11803472

申请日：2007-05-15

申请人： Daniel Feezell ,  Daniel Cohen ,  Robert Farrell ,  Masahiro Ishida ,  Shuji Nakamura

发明人： Daniel Feezell ,  Daniel Cohen ,  Robert Farrell ,  Masahiro Ishida ,  Shuji Nakamura

IPC分类号： H01S5/00 ,  H01S3/04

CPC分类号： H01S5/18341 ,  H01S5/0207 ,  H01S5/0421 ,  H01S5/0425 ,  H01S5/18308 ,  H01S5/18388 ,  H01S5/32341

摘要： A vertical-cavity surface-emitting laser (VCSEL) comprising a low-loss thin metal contact and current spreading layer within the optical cavity that provides for improved ohmic contact and lateral current distribution, a substrate including a plano-concave optical cavity, a (Ga,In,Al)N multiple quantum well (MQW) active region contained within the optical cavity that generates light when injected by an electrical current, and an integrated micromirror fabricated onto the substrate that provides for optical mode control of the light generated by the active region. A relatively simple process is used to fabricate the VCSEL.

摘要翻译： 一种垂直腔表面发射激光器（VCSEL），其包括光腔内的低损耗薄金属接触和电流扩展层，其提供改善的欧姆接触和横向电流分布;衬底，包括平凹光学腔，（ Ga，In，Al）N多量子阱（MQW）有源区，其包含在通过电流注入时产生光的光腔内;以及集成微镜，其被制造到基板上，该微镜提供对由 活跃区域。 使用相对简单的过程来制造VCSEL。