公开(公告)号：US20110183482A1

公开(公告)日：2011-07-28

申请号：US13015838

申请日：2011-01-28

Applicant: Sung-Sam LEE ,  Min-Hee CHO

Inventor： Sung-Sam LEE ,  Min-Hee CHO

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/78

Abstract: A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.

Abstract translation: 公开了晶体管和晶体管的制造方法。 晶体管设置在由隔离区域限定的衬底的有源区域中，并且包括栅极电极和相关的源极/漏极区域。 隔离区域包括上部隔离区域和下部隔离区域，其中上部隔离区域形成有具有至少部分至少部分为正形状的侧壁。

公开(公告)号：US20080157194A1

公开(公告)日：2008-07-03

申请号：US12025877

申请日：2008-02-05

Applicant: Sung-Sam LEE ,  Min-Hee CHO

Inventor： Sung-Sam LEE ,  Min-Hee CHO

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66621 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/78

Abstract: A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.

Abstract translation: 公开了晶体管和晶体管的制造方法。 晶体管设置在由隔离区域限定的衬底的有源区域中，并且包括栅极电极和相关的源极/漏极区域。 隔离区域包括上部隔离区域和下部隔离区域，其中上部隔离区域形成有具有至少部分至少部分为正形状的侧壁。

公开(公告)号：US20080054353A1

公开(公告)日：2008-03-06

申请号：US11849900

申请日：2007-09-04

Applicant: Ho-Jin OH ,  Sung-Sam LEE ,  Bong-Cheol KIM

Inventor： Ho-Jin OH ,  Sung-Sam LEE ,  Bong-Cheol KIM

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/06

CPC classification number: H01L21/823437 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/7834

Abstract: A semiconductor device includes a semiconductor substrate and recess trenches formed on the semiconductor substrate. The recess trenches are arranged to extend along a first direction. Terminal regions of adjacent ones of the recess trenches are offset relative to each other along a second direction substantially perpendicular to the first direction.

Abstract translation: 半导体器件包括半导体衬底和形成在半导体衬底上的凹槽。 凹槽被布置成沿着第一方向延伸。 相邻的凹槽的端子区域沿着基本上垂直于第一方向的第二方向相对于彼此偏移。

公开(公告)号：US20070042583A1

公开(公告)日：2007-02-22

申请号：US11463812

申请日：2006-08-10

Applicant: Sung-Ho JANG ,  Sang-Ho SONG ,  Sung-Sam LEE ,  Min-Sung KANG ,  Won-Tae PARK ,  Min-Young SHIM

Inventor： Sung-Ho JANG ,  Sang-Ho SONG ,  Sung-Sam LEE ,  Min-Sung KANG ,  Won-Tae PARK ,  Min-Young SHIM

IPC: H01L21/3205

CPC classification number: H01L21/76897 ,  H01L27/10876 ,  H01L29/7834

Abstract: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

Abstract translation: 根据一个实施例，在衬底的沟道区上形成包括栅极绝缘图案，栅极图案和栅极掩模的栅极结构，以形成半导体器件。 在栅极结构的表面上形成间隔物。 在包括栅极结构的基板上形成绝缘层间图案，并且通过与基板的杂质区域对应的绝缘层间图案形成开口。 在开口中形成导电图案，其顶表面高于绝缘层间图案的顶表面。 因此，导电图案的上部从绝缘层间图案突出。 在绝缘层间图案上形成封盖图案，并且用封盖图案覆盖导电图案的突出部分的侧壁。 因此，封盖图案补偿了栅极掩模的厚度减小。

公开(公告)号：US20060263991A1

公开(公告)日：2006-11-23

申请号：US11383141

申请日：2006-05-12

Applicant: Sung-Sam LEE ,  Gyo-Young JIN ,  Yun-Gi KIM

Inventor： Sung-Sam LEE ,  Gyo-Young JIN ,  Yun-Gi KIM

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L21/76232

Abstract: In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.

Abstract translation: 在一个实施例中，半导体器件具有由形成在STI沟槽内部的隔离层限定的有源区，该隔离层包括上沟槽和下沟槽，所述上沟槽和下沟槽在所述上沟槽下方具有基本弯曲的横截面轮廓，使得所述下沟槽处于连通状态 与上沟槽。 由于上沟槽具有以正斜率渐缩的侧壁，因此当用绝缘层填充上沟槽时，可以获得良好的间隙填充性能。 通过在下沟槽中形成空隙，隔离层底部的介电常数低于氧化物层的介电常数，从而提高隔离性能。 隔离层包括仅在上沟槽内形成的第一绝缘层，并且以间隔物的形式覆盖上沟槽的内壁。

公开(公告)号：US20070108516A1

公开(公告)日：2007-05-17

申请号：US11552359

申请日：2006-10-24

Applicant: Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

Inventor： Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

IPC: H01L29/94

CPC classification number: H01L21/823437 ,  H01L21/823481

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract translation: 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

公开(公告)号：US20080036016A1

公开(公告)日：2008-02-14

申请号：US11871876

申请日：2007-10-12

Applicant: Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

Inventor： Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

IPC: H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823481

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract translation: 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。