TRANSISTORS WITH LATERALLY EXTENDED ACTIVE REGIONS AND METHODS OF FABRICATING SAME
    1.
    发明申请
    TRANSISTORS WITH LATERALLY EXTENDED ACTIVE REGIONS AND METHODS OF FABRICATING SAME 失效
    具有横向扩展的活动区域的晶体管及其制造方法

    公开(公告)号:US20110183482A1

    公开(公告)日:2011-07-28

    申请号:US13015838

    申请日:2011-01-28

    CPC classification number: H01L29/66621 H01L21/76232 H01L21/823481 H01L29/78

    Abstract: A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.

    Abstract translation: 公开了晶体管和晶体管的制造方法。 晶体管设置在由隔离区域限定的衬底的有源区域中,并且包括栅极电极和相关的源极/漏极区域。 隔离区域包括上部隔离区域和下部隔离区域,其中上部隔离区域形成有具有至少部分至少部分为正形状的侧壁。

    TRANSISTORS WITH LATERALLY EXTENDED ACTIVE REGIONS AND METHODS OF FABRICATING SAME
    2.
    发明申请
    TRANSISTORS WITH LATERALLY EXTENDED ACTIVE REGIONS AND METHODS OF FABRICATING SAME 失效
    具有横向扩展的活动区域的晶体管及其制造方法

    公开(公告)号:US20080157194A1

    公开(公告)日:2008-07-03

    申请号:US12025877

    申请日:2008-02-05

    CPC classification number: H01L29/66621 H01L21/76232 H01L21/823481 H01L29/78

    Abstract: A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an upper isolation region and an lower isolation region, wherein the upper isolation region is formed with sidewalls having, at least in part, a positive profile.

    Abstract translation: 公开了晶体管和晶体管的制造方法。 晶体管设置在由隔离区域限定的衬底的有源区域中,并且包括栅极电极和相关的源极/漏极区域。 隔离区域包括上部隔离区域和下部隔离区域,其中上部隔离区域形成有具有至少部分至少部分为正形状的侧壁。

    RECESSED GATE TRANSISTOR STRUCTURE AND METHOD OF FORMING THE SAME
    3.
    发明申请
    RECESSED GATE TRANSISTOR STRUCTURE AND METHOD OF FORMING THE SAME 有权
    闭合闸门晶体管结构及其形成方法

    公开(公告)号:US20070069268A1

    公开(公告)日:2007-03-29

    申请号:US11560756

    申请日:2006-11-16

    Abstract: Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.

    Abstract translation: 嵌入栅极晶体管结构及其制造方法即使在形成栅极时产生不对准,也可以通过在其间形成绝缘层来防止形成在非有源区上的栅极导电层与有源区之间的短路。 该方法和结构降低了门之间的电容。 该方法包括在半导体衬底的预定区域上形成用于限定有源区和非有源区的器件隔离膜。 第一和第二绝缘层形成在基板的整个表面上。 在有源区域的一部分中形成凹部。 在凹部内形成栅极绝缘层,然后在凹部内形成第一栅极导电层。 第二栅极导电层形成在第二绝缘层和第一栅极导电层上。 随后,形成源/漏区。

    SYSTEM AND METHOD FOR ALLOCATING RESOURCES IN A COMMUNICATION SYSTEM
    5.
    发明申请
    SYSTEM AND METHOD FOR ALLOCATING RESOURCES IN A COMMUNICATION SYSTEM 审中-公开
    在通信系统中分配资源的系统和方法

    公开(公告)号:US20090067379A1

    公开(公告)日:2009-03-12

    申请号:US12205111

    申请日:2008-09-05

    Abstract: A method and system for allocating feedback resources in a communication system are provided, in which a Base Station (BS) allocates a first feedback resource area for ACKnowledgment/Negative ACKnowledgment (ACK/NACK) messages for general packets and a second feedback resource area for ACK/NACK messages for fixed packets, transmits the general packets and the fixed packets to at least one Mobile Station (MS), receives ACK/NACK messages in the first and second feedback resource areas, and when at least one of the fixed packets is canceled from transmission after the transmission of the general packets and the fixed packets, transmits a bitmap message to the at least one MS indicating use or non-use of the second feedback resource area for each packet, to enable a feedback resource area allocated for the canceled fixed packet to be allocated to an ACK/NACK message for an additionally generated general packet.

    Abstract translation: 提供了一种用于在通信系统中分配反馈资源的方法和系统,其中基站(BS)为用于通用分组的确认/否定确认(ACK / NACK)消息分配第一反馈资源区域,并且为第 对于固定分组的ACK / NACK消息,将通用分组和固定分组发送到至少一个移动台(MS),在第一和第二反馈资源区域中接收ACK / NACK消息,并且当至少一个固定分组是 在发送通用分组和固定分组之后从传输中取消,向每个分组发送指示对每个分组使用或不使用第二反馈资源区域的至少一个MS的位图消息,以使得能够为 取消的固定分组被分配给用于另外生成的通用分组的ACK / NACK消息。

    Method of forming dual gate dielectric layer
    6.
    发明申请
    Method of forming dual gate dielectric layer 有权
    形成双栅介电层的方法

    公开(公告)号:US20070102767A1

    公开(公告)日:2007-05-10

    申请号:US11616836

    申请日:2006-12-27

    CPC classification number: H01L21/823481 H01L21/76229 H01L21/823462

    Abstract: A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer is formed on a first region. The semiconductor device also includes a second dielectric layer having a dielectric constant higher than that of the first dielectric layer. The second dielectric layer is formed on both the first region and a second region.

    Abstract translation: 半导体器件包括提高半导体器件的性能的双栅介质层。 半导体器件包括在半导体衬底上具有预定厚度的第一电介质层。 第一介电层形成在第一区域上。 半导体器件还包括具有高于第一介电层的介电常数的介电常数的第二电介质层。 第二介电层形成在第一区域和第二区域两者上。

    APPARATUS AND METHOD FOR HYBRID AUTOMATIC REPEAT REQUEST SIGNALING IN BROADBAND WIRELESS COMMUNICATION SYSTEM
    7.
    发明申请
    APPARATUS AND METHOD FOR HYBRID AUTOMATIC REPEAT REQUEST SIGNALING IN BROADBAND WIRELESS COMMUNICATION SYSTEM 失效
    宽带无线通信系统中混合自动重发信号的装置和方法

    公开(公告)号:US20080186886A1

    公开(公告)日:2008-08-07

    申请号:US12025943

    申请日:2008-02-05

    CPC classification number: H04L1/1896 H04L1/1812 H04L2001/0093

    Abstract: An apparatus and method for Hybrid Automatic Repeat reQuest (HARQ) signaling in a broadband wireless communication system are provided. A communication method of a Base Station (BS) includes transmitting a Fixed Allocation (FA) message containing bitmap index information for all Mobile Stations (MSs) allocated with fixed resources; and transmitting bitmap information indicating whether packets to be transmitted to the MSs are Retransmission (Rtx) packets or new packets. Accordingly, when HARQ is carried out using a fixed resource allocation scheme, a bitmap is used to indicate whether HARQ packets transmitted in a current frame are new packets or Rtx packets. Therefore, a receiving end can be prevented from incorrectly decoding the packets.

    Abstract translation: 提供了一种用于宽带无线通信系统中的混合自动重复请求(HARQ)信令的装置和方法。 基站(BS)的通信方法包括发送包含分配有固定资源的所有移动站(MS)的位图索引信息的固定分配(FA)消息; 以及发送指示要发送给MS的分组的位图信息是重传(Rtx)分组还是新分组。 因此,当使用固定资源分配方案执行HARQ时,使用位图来指示当前帧中发送的HARQ分组是新分组还是Rtx分组。 因此,可以防止接收端错误地解码分组。

    SEMICONDUCTOR DEVICE HAVING STORAGE NODES ON ACTIVE REGIONS AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE HAVING STORAGE NODES ON ACTIVE REGIONS AND METHOD OF FABRICATING THE SAME 审中-公开
    具有活性区域的存储点的半导体器件及其制造方法

    公开(公告)号:US20090073736A1

    公开(公告)日:2009-03-19

    申请号:US12211412

    申请日:2008-09-16

    CPC classification number: H01L29/66621 H01L27/10876 H01L29/4236

    Abstract: A semiconductor device includes an active region in a semiconductor substrate, having first, second and third regions sequentially arranged in the active region. An inactive region in the semiconductor substrate defines the active region. Gate patterns, partially buried in the active and inactive regions, are positioned between the first and second regions or between the second and third regions, intersecting the active region at right angles. A bit line pattern intersects the gate patterns at right angles and overlaps the inactive region, the bit line pattern including a region electrically connected to the second region of the active region. An interlayer insulating layer covers the gate patterns. Storage nodes on the interlayer insulating layer are electrically connected to the active region. A first storage node overlaps the first region and the inactive region and a second storage node overlaps the third region, the inactive region and the bit line pattern.

    Abstract translation: 半导体器件包括在半导体衬底中的有源区,具有顺序地布置在有源区中的第一,第二和第三区。 半导体衬底中的非活性区限定有源区。 部分地埋在有源和非活动区域中的栅极图案位于第一和第二区域之间,或位于第二和第三区域之间,与有源区域成直角相交。 位线图案与栅极图案成直角相交并且与非活性区域重叠,位线图案包括电连接到有源区域的第二区域的区域。 层间绝缘层覆盖栅极图案。 层间绝缘层上的存储节点与有源区电连接。 第一存储节点与第一区域和非活动区域重叠,并且第二存储节点与第三区域,非活动区域和位线图案重叠。

    SEMICONDUCTOR DEVICES HAVING A RECESSED ACTIVE EDGE AND METHODS OF FABRICATING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICES HAVING A RECESSED ACTIVE EDGE AND METHODS OF FABRICATING THE SAME 有权
    具有接近活跃边缘的半导体器件及其制造方法

    公开(公告)号:US20070029619A1

    公开(公告)日:2007-02-08

    申请号:US11462949

    申请日:2006-08-07

    CPC classification number: H01L29/78 H01L21/28114 H01L29/42376 H01L29/66621

    Abstract: A semiconductor device having a recessed active edge is provided. The semiconductor devices include an isolation layer disposed in a substrate to define an active region. A gate electrode is disposed to cross over the active region. A source region and a drain region are disposed in the active region on both sides of the gate electrode. A recessed region is disposed under the gate electrode and on an edge of the active region adjacent to the isolation layer. A bottom of the recessed region may be sloped down toward the isolation layer. The gate electrode may further extend into and fill the recessed region. That is, a gate extension may be disposed in the recessed region. A method of fabricating the semiconductor device is also provided.

    Abstract translation: 提供具有凹入的有效边缘的半导体器件。 半导体器件包括设置在衬底中以限定有源区的隔离层。 栅电极设置成跨越有源区。 源极区域和漏极区域设置在栅电极两侧的有源区域中。 凹陷区域设置在栅电极下方和与隔离层相邻的有源区域的边缘上。 凹陷区域的底部可朝向隔离层倾斜。 栅电极可以进一步延伸并填充凹陷区域。 也就是说,可以在凹入区域中设置栅极延伸部。 还提供了制造半导体器件的方法。

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