公开(公告)号：US08895400B2

公开(公告)日：2014-11-25

申请号：US13473751

申请日：2012-05-17

申请人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

IPC分类号： H01L21/331 ,  H01L27/108 ,  H01L21/74 ,  H01L21/311

CPC分类号： H01L27/10891 ,  H01L21/743 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

摘要翻译： 半导体器件包括具有限定在其中的单元区域和外围电路区域的半导体衬底。 掩埋字线设置在单元区域中的基板中，并且具有比单元区域中的单元有源区域的顶表面低的顶表面。 栅极线设置在外围电路区域中的衬底上。 字线互连设置在外围电路区域中的衬底中，字线互连包括接触掩埋字线的第一部分，并且具有低于电池有源区的顶表面的顶表面和重叠的第二部分 通过并与栅极线接触。

公开(公告)号：US08633375B2

公开(公告)日：2014-01-21

申请号：US13165058

申请日：2011-06-21

申请人： Ihn Gee Baik ,  Yun Gi Kim ,  Jin Wook Lee ,  Jin-Soo Mun

发明人： Ihn Gee Baik ,  Yun Gi Kim ,  Jin Wook Lee ,  Jin-Soo Mun

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01L31/02363 ,  H01L31/022425 ,  Y02E10/50

摘要： A solar cell and method of manufacturing the same includes a semiconductor substrate having a textured surface and including a plurality of recess portions and a plurality of flat portions, an emitter layer in the plurality of recess portions, a first doping region in at least one of the plurality of flat portions, and doped with a first conductive type impurity selected from one of p-type and n-type impurities, a second doping region in at least one of the plurality of flat portions, and doped with a second conductive type impurity selected from one of p-type and n-type impurities that differs from the first conductive type impurity, and first and second electrodes electrically connected to the first and second doping regions, respectively. The distance between the emitter layer and the first doping region is different from the distance between the emitter layer and the second doping region.

摘要翻译： 一种太阳能电池及其制造方法包括：具有纹理表面的半导体基板，具有多个凹部和多个平坦部，多个凹部内的发射极层， 多个平坦部分，并且掺杂有选自p型和n型杂质之一的第一导电类型杂质，在所述多个平坦部分中的至少一个中的第二掺杂区域，并且掺杂有第二导电类型杂质 选自与第一导电类型杂质不同的p型和n型杂质之一，以及分别电连接到第一和第二掺杂区的第一和第二电极。 发射极层和第一掺杂区域之间的距离不同于发射极层和第二掺杂区域之间的距离。

公开(公告)号：US08440489B2

公开(公告)日：2013-05-14

申请号：US12828701

申请日：2010-07-01

申请人： Dong-Kyun Kim ,  Yun-Gi Kim ,  Jin-Wook Lee ,  Hwa-Young Ko

发明人： Dong-Kyun Kim ,  Yun-Gi Kim ,  Jin-Wook Lee ,  Hwa-Young Ko

IPC分类号： H01L21/00

CPC分类号： H01L31/02168 ,  H01L31/022425 ,  H01L31/056 ,  H01L31/0682 ,  H01L31/1804 ,  Y02E10/52 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of manufacturing a solar cell includes providing a semiconductor substrate; disposing a reflection layer on one side of the semiconductor substrate, wherein the disposing the reflection layer comprises implanting gas into a surface of the one side of the semiconductor substrate and heating the gas; disposing an n+ region and a p+ region separated from each other on the other opposite facing side of the semiconductor substrate; disposing a first electrode connected to the n+ region; and disposing a second electrode connected to the p+ region.

摘要翻译： 一种制造太阳能电池的方法包括提供半导体衬底; 在半导体衬底的一侧上设置反射层，其中设置反射层包括将气体注入到半导体衬底的一侧的表面中并加热气体; 在所述半导体衬底的另一个相对的面上设置彼此分离的n +区域和p +区域; 设置连接到n +区的第一电极; 以及设置连接到p +区域的第二电极。

公开(公告)号：US07939408B2

公开(公告)日：2011-05-10

申请号：US12970475

申请日：2010-12-16

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

摘要翻译： 提供了一种用于2位操作的非易失性存储器件及其制造方法。 非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。 有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

公开(公告)号：US20110086483A1

公开(公告)日：2011-04-14

申请号：US12970475

申请日：2010-12-16

申请人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

发明人： Byung-yong Choi ,  Dong-gun Park ,  Yun-gi Kim ,  Choong-ho Lee ,  Young-mi Lee ,  Hye-jin Cho

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

摘要翻译： 提供了一种用于2位操作的非易失性存储器件及其制造方法。 非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。 有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

公开(公告)号：US07629745B2

公开(公告)日：2009-12-08

申请号：US11554061

申请日：2006-10-30

申请人： Yun Gi Kim

发明人： Yun Gi Kim

IPC分类号： H01J17/49

CPC分类号： H01J11/36 ,  H01J11/12 ,  H01J2211/361 ,  H01J2211/363

摘要： A plasma display apparatus is provided. The plasma display apparatus includes an upper substrate, a lower substrate that faces the upper substrate, and barrier ribs formed on the lower substrate to partition off discharge cells. At least one groove having a width no less than 0.1 times and no more than 0.8 times the width of the barrier rib is formed on the barrier rib. Therefore, it is possible to reduce a capacitance value between address electrodes and reduce reactive power formed between the electrodes so that it is possible to improve the discharge efficiency of the panel.

摘要翻译： 提供了一种等离子体显示装置。 等离子体显示装置包括上基板，面向上基板的下基板和形成在下基板上的隔板以分隔放电单元。 在隔壁上形成有宽度不小于阻挡肋宽度的0.1倍且不大于0.8倍的至少一个槽。 因此，可以减小寻址电极之间的电容值并且减小电极之间形成的无功功率，从而可以提高面板的放电效率。

公开(公告)号：US07622778B2

公开(公告)日：2009-11-24

申请号：US11383141

申请日：2006-05-12

申请人： Sung-Sam Lee ,  Gyo-Young Jin ,  Yun-Gi Kim

发明人： Sung-Sam Lee ,  Gyo-Young Jin ,  Yun-Gi Kim

IPC分类号： H01L23/62

CPC分类号： H01L21/76232

摘要： In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.

摘要翻译： 在一个实施例中，半导体器件具有由形成在STI沟槽内部的隔离层限定的有源区，该隔离层包括上沟槽和下沟槽，所述上沟槽和下沟槽在所述上沟槽下方具有基本弯曲的横截面轮廓，使得所述下沟槽处于连通状态 与上沟槽。 由于上沟槽具有以正斜率渐缩的侧壁，因此当用绝缘层填充上沟槽时，可以获得良好的间隙填充性能。 通过在下沟槽中形成空隙，隔离层底部的介电常数低于氧化物层的介电常数，从而提高隔离性能。 隔离层包括仅在上沟槽内形成的第一绝缘层，并且以间隔物的形式覆盖上沟槽的内壁。

公开(公告)号：US20080277646A1

公开(公告)日：2008-11-13

申请号：US12179068

申请日：2008-07-24

申请人： Ki-Nam Kim ,  Yun-Gi Kim

发明人： Ki-Nam Kim ,  Yun-Gi Kim

IPC分类号： H01L29/06 ,  H01L29/94

CPC分类号： H01L29/78642 ,  B82Y10/00 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/938

摘要： A vertical type nanotuhe semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.

摘要翻译： 一种垂直型纳米管半导体器件，包括纳米管位线，设置在基板上并且与该基板并联并且由具有导电性质的纳米管构成，并且纳米管极与所述位线垂直地连接到所述基板并提供通道 哪些运营商迁移。 通过使用由纳米管构成的位线制造半导体器件，防止了位线的电连接的切断，并且可以提高半导体器件的集成密度。

公开(公告)号：US20080029810A1

公开(公告)日：2008-02-07

申请号：US11563365

申请日：2006-11-27

申请人： Bong Soo Kim ,  Yun-Gi Kim ,  Hyeoung-Won Seo

发明人： Bong Soo Kim ,  Yun-Gi Kim ,  Hyeoung-Won Seo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L29/66621

摘要： Methods of fabricating semiconductor devices capable of maintaining a liner on both sidewalls of an active region overlapping a gate are provided. An isolation trench defining an active region is formed in a semiconductor substrate. A liner is formed on sidewalls of the active region. An isolation layer filling the isolation trench is formed. A hard mask pattern is formed on the semiconductor substrate having the liner and the isolation layer. A gate trench crossing the active region is formed using the hard mask pattern as an etching mask. A gate is formed in the gate trench. After forming the gate, the hard mask pattern is removed. A gate capping pattern is formed on the gate.

摘要翻译： 提供了制造能够在与栅极重叠的有源区域的两侧壁上保持衬垫的半导体器件的制造方法。 在半导体衬底中形成限定有源区的隔离沟槽。 衬垫形成在活性区域的侧壁上。 形成了填充隔离沟槽的隔离层。 在具有衬垫和隔离层的半导体衬底上形成硬掩模图案。 使用硬掩模图案作为蚀刻掩模形成与有源区交叉的栅极沟槽。 栅极形成在栅极沟槽中。 在形成栅极之后，去除硬掩模图案。 栅极上形成栅极覆盖图案。

公开(公告)号：US20070257007A1

公开(公告)日：2007-11-08

申请号：US11808515

申请日：2007-06-11

申请人： Yun-gi Kim ,  Yong-shik Park ,  Sung-joon Park

发明人： Yun-gi Kim ,  Yong-shik Park ,  Sung-joon Park

IPC分类号： G01D15/00 ,  C23F1/00 ,  C03C25/68

CPC分类号： B41J2/14129 ,  B41J2/1404 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1642 ,  B41J2/1646

摘要： A bubble-ink jet print head includes: a substrate having ink chambers to store ink and resistance heat emitting bodies to heat ink disposed thereover; and an ink supply passage which penetrates the substrate and which is connected with the ink chambers. The ink supply passage includes: a first trench formed at a first surface of the substrate in a first pattern having a separating distance from at least one of inlets of the ink chambers and connecting portions between the adjacent ink chambers, the first surface of the substrate having the ink chambers disposed thereover, and a second trench formed at a second surface of the substrate in a second pattern, having one of an area equal to and an area smaller than that of the first trench in the range of the first pattern of the first trench, and in communication with the first trench.

摘要翻译： 气泡喷墨打印头包括：具有存储墨的墨室和用于加热设置在其上的墨的电阻发热体的基板; 以及穿过基板并与墨水室连接的供墨通道。 供墨通道包括：第一沟槽，以第一图案形成在基板的第一表面处，该第一图案具有与墨室的入口和相邻墨室之间的连接部分中的至少一个的分隔距离，基板的第一表面 具有设置在其上的墨水室和形成在第二图案的基板的第二表面处的第二沟槽，其具有与第一图案的第一图案的范围内的第一沟槽的面积等于或小于第一沟槽的面积的面积 第一沟槽，并与第一沟槽沟通。