公开(公告)号：US07476924B2

公开(公告)日：2009-01-13

申请号：US11550553

申请日：2006-10-18

申请人： Je-Min Park ,  Ho-Jin Oh

发明人： Je-Min Park ,  Ho-Jin Oh

IPC分类号： H01L27/108

CPC分类号： H01L27/10888 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76889

摘要： A semiconductor device having a recessed landing pad includes a semiconductor substrate and a lower interlayer dielectric layer disposed on the semiconductor substrate. A first landing pad is disposed through the lower interlayer dielectric layer to be in contact with the semiconductor substrate. A second landing pad is disposed through the lower interlayer dielectric layer to also be in contact with the semiconductor substrate. A metal silicide layer is disposed on the second landing pad. The metal silicide layer is disposed lower than a top surface of the first landing pad. An intermediate interlayer dielectric layer is disposed on the lower interlayer dielectric layer. A conductive line is disposed on the intermediate interlayer dielectric layer. A contact plug is disposed between the conductive line and the metal silicide layer. A designed contact area between the metal silicide layer and the contact plug is protected against inadvertent etching.

摘要翻译： 具有凹入的着陆焊盘的半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。 第一着陆焊盘通过下层间介质层设置成与半导体衬底接触。 第二着陆焊盘通过下层间介质层设置成也与半导体衬底接触。 金属硅化物层设置在第二着陆焊盘上。 金属硅化物层设置成比第一着陆焊盘的顶表面低。 中间层间介电层设置在下层间介质层上。 导电线设置在中间层间电介质层上。 接触插头设置在导电线和金属硅化物层之间。 金属硅化物层和接触插塞之间的设计的接触区域被保护以防止无意的蚀刻。

公开(公告)号：US20080054354A1

公开(公告)日：2008-03-06

申请号：US11849928

申请日：2007-09-04

申请人： Ho-Jin OH ,  Jee-Eun JUNG

发明人： Ho-Jin OH ,  Jee-Eun JUNG

IPC分类号： H01L29/78 ,  G03F9/00 ,  H01L21/336

CPC分类号： H01L29/66621 ,  G03F1/50 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/7834

摘要： A photo mask, a semiconductor integrated circuit, and a method of manufacturing the same are provided. The photo mask includes light transmitting rows and recess trenches, respectively, that include a short region in every other light transmitting row. In the semiconductor integrated circuit, the short region may include a dummy transistor so that short-circuiting bridges that may occur between adjacent recess trenches will not adversely affect the operations of the semiconductor integrated circuit.

摘要翻译： 提供了一种光掩模，半导体集成电路及其制造方法。 光掩模包括分别包括在每隔一个光传输行中的短区域的透光行和凹槽。 在半导体集成电路中，短区域可以包括虚设晶体管，使得可能在相邻凹槽之间发生的短路桥不会不利地影响半导体集成电路的操作。

公开(公告)号：US07745899B2

公开(公告)日：2010-06-29

申请号：US11832270

申请日：2007-08-01

申请人： Ho-Jin Oh ,  Je-Min Park ,  Jee-Eun Jung

发明人： Ho-Jin Oh ,  Je-Min Park ,  Jee-Eun Jung

IPC分类号： H01L29/423 ,  H01L21/3205

CPC分类号： G03F1/70 ,  G03F1/00 ,  H01L29/4238

摘要： An embodiment of a photomask for forming gate lines and a method of manufacturing semiconductor devices using the photomask is disclosed. The photomask includes a photomask substrate, gate line mask patterns that define gate lines that cross at least one active region on a semiconductor substrate, and that are arranged in parallel, gate tab mask patterns formed on both sides of each gate line mask pattern, and joints formed between adjacent gate tab mask patterns, and that include a separation region. A relatively large gate tab mask pattern can be formed using the photomask. And a short channel effect at the boundary of the active region can be improved with the large gate tab mask pattern, so the characteristics and reliability of the semiconductor devices can be improved.

摘要翻译： 公开了用于形成栅极线的光掩模的实施例和使用光掩模制造半导体器件的方法。 光掩模包括光掩模基板，限定栅极线的栅极线掩模图案，栅极线与半导体衬底上的至少一个有源区交叉并且平行布置，形成在每个栅极线掩模图案的两侧上的栅极掩模图案，以及 在相邻的闸板掩模图案之间形成的接头，并且包括分离区域。 可以使用光掩模形成相对较大的栅极贴片掩模图案。 并且通过大的栅极片掩模图案可以改善有源区边界的短沟道效应，从而可以提高半导体器件的特性和可靠性。

公开(公告)号：US20080044989A1

公开(公告)日：2008-02-21

申请号：US11832270

申请日：2007-08-01

申请人： Ho-Jin OH ,  Je-Min PARK ,  Jee-Eun JUNG

发明人： Ho-Jin OH ,  Je-Min PARK ,  Jee-Eun JUNG

IPC分类号： G03C5/00 ,  H01L21/3205

CPC分类号： G03F1/70 ,  G03F1/00 ,  H01L29/4238

摘要： An embodiment of a photomask for forming gate lines and a method of manufacturing semiconductor devices using the photomask is disclosed. The photomask includes a photomask substrate, gate line mask patterns that define gate lines that cross at least one active region on a semiconductor substrate, and that are arranged in parallel, gate tab mask patterns formed on both sides of each gate line mask pattern, and joints formed between adjacent gate tab mask patterns, and that include a separation region. A relatively large gate tab mask pattern can be formed using the photomask. And a short channel effect at the boundary of the active region can be improved with the large gate tab mask pattern, so the characteristics and reliability of the semiconductor devices can be improved.

摘要翻译： 公开了用于形成栅极线的光掩模的实施例和使用光掩模制造半导体器件的方法。 光掩模包括光掩模基板，限定栅极线的栅极线掩模图案，栅极线与半导体衬底上的至少一个有源区交叉并且平行布置，形成在每个栅极线掩模图案的两侧上的栅极掩模图案，以及 在相邻的闸板掩模图案之间形成的接头，并且包括分离区域。 可以使用光掩模形成相对较大的栅极贴片掩模图案。 并且通过大的栅极片掩模图案可以改善有源区边界的短沟道效应，从而可以提高半导体器件的特性和可靠性。

公开(公告)号：US20070152257A1

公开(公告)日：2007-07-05

申请号：US11550553

申请日：2006-10-18

申请人： Je-Min Park ,  Ho-Jin Oh

发明人： Je-Min Park ,  Ho-Jin Oh

IPC分类号： H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10888 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76889

摘要： A semiconductor device having a recessed landing pad includes a semiconductor substrate and a lower interlayer dielectric layer disposed on the semiconductor substrate. A first landing pad is disposed through the lower interlayer dielectric layer to be in contact with the semiconductor substrate. A second landing pad is disposed through the lower interlayer dielectric layer to also be in contact with the semiconductor substrate. A metal silicide layer is disposed on the second landing pad. The metal silicide layer is disposed lower than a top surface of the first landing pad. An intermediate interlayer dielectric layer is disposed on the lower interlayer dielectric layer. A conductive line is disposed on the intermediate interlayer dielectric layer. A contact plug is disposed between the conductive line and the metal silicide layer. A designed contact area between the metal silicide layer and the contact plug is protected against inadvertent etching.

摘要翻译： 具有凹入的着陆焊盘的半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。 第一着陆焊盘通过下层间介质层设置成与半导体衬底接触。 第二着陆焊盘通过下层间介质层设置成也与半导体衬底接触。 金属硅化物层设置在第二着陆焊盘上。 金属硅化物层设置成比第一着陆焊盘的顶表面低。 中间层间介电层设置在下层间介质层上。 导电线设置在中间层间电介质层上。 接触插头设置在导电线和金属硅化物层之间。 金属硅化物层和接触插塞之间的设计的接触区域被保护以防止无意的蚀刻。

公开(公告)号：US20080054353A1

公开(公告)日：2008-03-06

申请号：US11849900

申请日：2007-09-04

申请人： Ho-Jin OH ,  Sung-Sam LEE ,  Bong-Cheol KIM

发明人： Ho-Jin OH ,  Sung-Sam LEE ,  Bong-Cheol KIM

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/7834

摘要： A semiconductor device includes a semiconductor substrate and recess trenches formed on the semiconductor substrate. The recess trenches are arranged to extend along a first direction. Terminal regions of adjacent ones of the recess trenches are offset relative to each other along a second direction substantially perpendicular to the first direction.

摘要翻译： 半导体器件包括半导体衬底和形成在半导体衬底上的凹槽。 凹槽被布置成沿着第一方向延伸。 相邻的凹槽的端子区域沿着基本上垂直于第一方向的第二方向相对于彼此偏移。

公开(公告)号：US20080029899A1

公开(公告)日：2008-02-07

申请号：US11712504

申请日：2007-03-01

申请人： Du-heon Song ,  Ho-jin Oh ,  Tai-heui Cho ,  Joo-hyun Lee

发明人： Du-heon Song ,  Ho-jin Oh ,  Tai-heui Cho ,  Joo-hyun Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L27/105 ,  H01L27/1052

摘要： A method of fabricating a semiconductor device, including forming contact pads in a first insulating layer on a substrate, forming a second insulating layer on the first insulating layer and on the contact pads, forming bit lines on the second insulating layer, the bit lines connected to a first plurality of the contact pads by bit line contact plugs, forming expanded contact holes in the second insulating layer between the bit lines, wherein the expanded contact holes are expanded toward the bit lines, and forming contact spacers on side walls of the expanded contact holes.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上的第一绝缘层中形成接触焊盘，在第一绝缘层和接触焊盘上形成第二绝缘层，在第二绝缘层上形成位线，连接位线 通过位线接触插塞连接到第一组多个接触焊盘，在位线之间的第二绝缘层中形成扩展的接触孔，其中扩大的接触孔朝向位线膨胀，并且在膨胀的 接触孔