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1.发明申请METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK 有权设计多状态恢复电路以将状态恢复到功率管理的功能块的方法公开(公告)号：US20090307637A1
公开(公告)日：2009-12-10
申请号：US12135250
申请日：2008-06-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/72
摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.
摘要翻译： 设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。 在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。 由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。 恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。 如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。
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2.发明授权Integrated circuit containing multi-state restore circuitry for restoring state to a power-managed functional block 有权包含用于将状态恢复到功率管理功能块的多状态恢复电路的集成电路公开(公告)号：US07821294B2
公开(公告)日：2010-10-26
申请号：US12135249
申请日：2008-06-09
IPC分类号： H03K19/173
CPC分类号： H03K19/0008 , H03K19/173
摘要： Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector.
摘要翻译： 多功能恢复电路，允许在功能块被重新加电时加载功率管理功能块的存储元件，使得功能块在功能块的电压升高之后实际上准备好运行。 多状态恢复电路包括恢复状态检测器，用于确定功能块的多个恢复状态中的哪一个可应用于功能块的特定重新启动。 多状态恢复电路还包括根据由恢复状态检测器确定的恢复状态来加载存储元件的恢复逻辑。
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3.发明授权Method of designing multi-state restore circuitry for restoring state to a power managed functional block 有权设计用于将状态恢复到功率管理功能块的多状态恢复电路的方法公开(公告)号：US08239791B2
公开(公告)日：2012-08-07
申请号：US12135250
申请日：2008-06-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/72
摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.
摘要翻译： 设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。 在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。 由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。 恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。 如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。
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4.发明申请INTEGRATED CIRCUIT CONTAINING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK 有权包含多状态恢复电路的集成电路，用于将状态恢复到功率管理的功能块公开(公告)号：US20090302889A1
公开(公告)日：2009-12-10
申请号：US12135249
申请日：2008-06-09
IPC分类号： H03K19/0175
CPC分类号： H03K19/0008 , H03K19/173
摘要： Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector.
摘要翻译： 多功能恢复电路，允许在功能块被重新加电时加载功率管理功能块的存储元件，使得功能块在功能块的电压升高之后实际上准备好运行。 多状态恢复电路包括恢复状态检测器，用于确定功能块的多个恢复状态中的哪一个可应用于功能块的特定重新启动。 多状态恢复电路还包括根据由恢复状态检测器确定的恢复状态来加载存储元件的恢复逻辑。
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公开(公告)号：US20120084540A1
公开(公告)日：2012-04-05
申请号：US13325307
申请日：2011-12-14
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3237 , G06F1/3243 , G06F9/3859 , G06F9/3873
摘要： A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译： 体现在设计过程中使用的机器可读，非暂时性存储介质中的设计结构包括用于动态地改变计算设备的流水线深度的系统。 该系统包括状态机，其基于要执行的处理功能来确定流水线架构的最佳长度。 响应于状态机的流水线序列控制器基于最佳长度改变管道的深度。 多个时钟分离器元件，每个与流水线架构中相应的多个锁存级相关联，并被连接到流水线序列控制器，并适于在功能模式，一个或多个时钟选通模式和直通冲洗 模式。 对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。
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6.发明授权Structure for dynamically adjusting pipelined data paths for improved power management 有权用于动态调整流水线数据路径以改善电源管理的结构公开(公告)号：US08086832B2
公开(公告)日：2011-12-27
申请号：US11869216
申请日：2007-10-09
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3237 , G06F1/3243 , G06F9/3859 , G06F9/3873
摘要： A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译： 体现在设计过程中使用的机器可读，非暂时性存储介质中的设计结构包括用于动态地改变计算设备的流水线深度的系统。 该系统包括状态机，其基于要执行的处理功能来确定流水线架构的最佳长度。 响应于状态机的流水线序列控制器基于最佳长度改变管道的深度。 多个时钟分离器元件，每个与流水线架构中相应的多个锁存级联相关联，连接到流水线序列控制器，并且适于在功能模式，一个或多个时钟选通模式和直通冲洗 模式。 对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。
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7.发明申请SYSTEM AND METHOD FOR DYNAMICALLY ADJUSTING PIPELINED DATA PATHS FOR IMPROVED POWER MANAGEMENT 审中-公开用于动态调整管道数据的系统和方法进行改进的电源管理公开(公告)号：US20070271449A1
公开(公告)日：2007-11-22
申请号：US11419388
申请日：2006-05-19
IPC分类号： G06F9/44
CPC分类号： G06F9/3869 , G06F9/3836 , G06F9/3859 , G06F9/3867 , G06F9/3873
摘要： A system for dynamically varying the pipeline depth of a computing device, depending upon at least one of computing function and workload, includes a state machine is configured to determine an optimum length of a pipeline architecture based on a processing function to be performed, and a pipeline sequence controller, responsive to the state machine, the pipeline sequence controller configured to vary the depth of the pipeline based on the determined optimum length. A plurality of clock splitter elements is associated with a corresponding plurality of latch stages in the pipeline architecture, the clock splitter elements coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译： 根据计算功能和工作负载中的至少一个动态地改变计算设备的流水线深度的系统包括状态机被配置为基于要执行的处理功能来确定流水线架构的最佳长度，以及 流水线序列控制器，响应于状态机，配置为基于所确定的最佳长度来改变管道的深度的流水线序列控制器。 多个时钟分离器元件与流水线架构中的对应的多个锁存级相关联，时钟分离器元件耦合到流水线序列控制器并且适于以功能模式操作，一个或多个时钟选通模式， 通过冲洗模式。 对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。
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8.发明授权Concurrent logical and physical construction of voltage islands for mixed supply voltage designs 失效用于混合电源电压设计的并联电压岛的逻辑和物理构造公开(公告)号：US06792582B1
公开(公告)日：2004-09-14
申请号：US09713829
申请日：2000-11-15
申请人： John M Cohn , Alvar A. Dean , David J. Hathaway , David E. Lackey , Thomas M. Lepsic , Susan K. Lichtensteiger , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M Cohn , Alvar A. Dean , David J. Hathaway , David E. Lackey , Thomas M. Lepsic , Susan K. Lichtensteiger , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into “bins”, which are areas of the design. In this way, a semiconductor chip design may be “sliced” into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.
摘要翻译： 公开了电压岛的逻辑和物理结构。 半导体芯片设计被划分为“箱”，这是设计的区域。 以这种方式，可以将半导体芯片设计“切片”成各种区域，然后将这些区域分配给各种电压电平。 每个仓可以被认为是电压岛。 设计中的电路可以添加到各个机箱中或从各个机箱中移除，从而增加或减少电路的速度和功率：如果将电路放入分配较高电压的箱体中，速度和功率会增加，速度和功率 如果将电路放置在具有较低电压的箱中，则减小。 还可以改变箱子的大小和位置。 通过迭代这些步骤，可以在满足速度限制和其他标准的同时满足最佳功耗。 本发明可应用于诸如退火放置工具的任何放置环境，其通过连续细化设计上的电路的位置并且其中可以中断放置过程以使逻辑的放置变化。
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9.发明授权公开(公告)号：US08499140B2
公开(公告)日：2013-07-30
申请号：US13325307
申请日：2011-12-14
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3237 , G06F1/3243 , G06F9/3859 , G06F9/3873
摘要： A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译： 体现在设计过程中使用的机器可读，非暂时性存储介质中的设计结构包括用于动态地改变计算设备的流水线深度的系统。 该系统包括状态机，其基于要执行的处理功能来确定流水线架构的最佳长度。 响应于状态机的流水线序列控制器基于最佳长度改变管道的深度。 多个时钟分离器元件，每个与流水线架构中相应的多个锁存级联相关联，连接到流水线序列控制器，并适于在功能模式，一个或多个时钟选通模式和直通冲洗 模式。 对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。
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公开(公告)号：US10067184B2
公开(公告)日：2018-09-04
申请号：US13294243
申请日：2011-11-11
IPC分类号： G01R27/28 , G01R31/00 , G01R31/14 , G01R31/317
摘要： A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of a set of voltages bins corresponding to frequency specification limits of an integrated circuit chip using functional testing of data paths of the integrated circuit chip.
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