公开(公告)号：US3846905A

公开(公告)日：1974-11-12

申请号：US37784473

申请日：1973-07-09

Applicant: TEXAS INSTRUMENTS INC

Inventor： HARPER J

IPC: H01L21/00 ,  H01L23/498 ,  H01L7/00

CPC classification number: H01L21/67144 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described in the assembly of integrated circuits that utilizes laser scribing while protecting the integrated circuit components and which enables use of automated machineoriented bonding techniques. The method includes aligning a slice of semiconductor material so that the integrated circuits thereon are oriented in a desired manner, the surface of the integrated circuits being covered with a protective wax and secured to a support. Infrared radiation is utilized to align the slice and to illuminate the scribe lines so they are detectable from the back surface of the slice. The slice is then separated along the scribe lines by partially cutting the slice from the back surface of the slice with a laser, the front surface of the slice being protected from the slag produced by the cutting action of the laser. Contacts on the respective chips are then bonded to metal leads by a method which enables utilization of a constant temperature source.

Abstract translation: 在组装使用激光划线同时保护集成电路部件的集成电路的组装中描述了一种方法，并且能够使用自动化的机器定向接合技术。 该方法包括对准半导体材料片，使得其上的集成电路以期望的方式取向，集成电路的表面被保护蜡覆盖并固定到支撑体上。 使用红外辐射来对齐切片并照亮划线，使得它们可以从切片的后表面检测。 然后通过用激光从切片的后表面部分切割切片，沿着划线分离切片，切片的前表面受到激光切割作用产生的熔渣的保护。 然后通过能够利用恒温源的方法将相应芯片上的触点接合到金属引线。

公开(公告)号：US3798135A

公开(公告)日：1974-03-19

申请号：US3798135D

申请日：1972-05-03

Applicant: TEXAS INSTRUMENTS INC

Inventor： PADDOCK A ,  MORRISON W ,  BRACKEN R ,  HARPER J

IPC: H01L21/301 ,  H01L21/00 ,  H01L21/283 ,  H01L21/306 ,  H01L21/316 ,  H01L21/3205 ,  H01L23/29 ,  H01L23/522 ,  C23B5/48 ,  H01L11/00

CPC classification number: H01L23/293 ,  H01L21/00 ,  H01L21/31687 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: ANODIC OXIDATION IS EMPLOYED IN THE FABRICATION OF INTEGRATED CIRCUITS TO PROVIDE PASSIVATION AND PROTECTION FROM ABRASION. IN ONE RESPECT OF THE INVENTION THE ANODIZED PASSIVATING LAYER IS SELECTIVELY ETCHED TO EXPOSE BONDNG PADS AND SCRIBE LINE AREAS. IN A DIFFERENT ASPECT OF THE INVENTION A METHOD FOR FABRICATING A MULTILEVEL INTERCONNECTED INTEGRATED CIRCUIT IS PROVIDED WHEREIN A LAYER OF ANOIDIC OXIDE IS FORMED TO COVER THE FIRST LEVEL OF INTERCONNECTS. A LAYER OF INSULATINNG MATERIAL IS THEN DEPOSTED OVER THE ANODIC OXIDE LAYER TO ADVANTAGEOUSLY REDUCE INTERLEVEL CAPACITANCE. FIRST LEVEL BONDING PADS AND SCRIBE LINE AREAS ARE EXPOSED. A CONDUCTIVE LAYER IS THEN DEPOSITED AND PATTERNED TO FORM THE SECOND LEVEL INTERCONNECTED PATTERN. THIS SECOND LEVEL INTERCONNECT MAY ALSO BE PROTECTED BY AN ANODIC OXIDATION OVERLAYER, IF DESIRED.