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公开(公告)号:US12113007B2
公开(公告)日:2024-10-08
申请号:US18230069
申请日:2023-08-03
发明人: BoYeon Kim , Whee-Won Lee , Myeong Su Kim , Sang Hyun Lee
IPC分类号: H01L23/498 , H01L23/00 , H10K59/131
CPC分类号: H01L23/49838 , H01L23/4985 , H01L24/16 , H10K59/131 , H01L2224/16225
摘要: A flexible circuit film includes the following elements: a base film; a first power input terminal, a second power input terminal, a first power output terminal, and a second power output terminal each disposed on the base film; an integrated circuit chip disposed between the first power input terminal and the first power output terminal and overlapping the base film; first power wiring disposed on the base film, connecting the first power input terminal to the first power output terminal, and including a first connection part; and second power wiring disposed on the base film, connecting the second power input terminal to the second power output terminal, and including a second connection part. The first connection part and the second connection part are disposed between the base film and the integrated circuit chip, overlap the integrated circuit chip, and are spaced from each other.
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公开(公告)号:US20240258226A1
公开(公告)日:2024-08-01
申请号:US18466278
申请日:2023-09-13
发明人: Fu LI
IPC分类号: H01L23/498
CPC分类号: H01L23/49838 , H01L23/49811 , H01L23/4985 , H01L25/0753
摘要: A chip-on-film includes a flexible substrate, a plurality of negative polarity pins, and a positive polarity pin. The plurality of negative polarity pins are arranged in a row in a first direction on the flexible substrate, and two adjacent negative polarity pins of the plurality of negative polarity pins are arranged in an interval. The positive polarity pin is disposed on the flexible substrate. The positive polarity pin is at least partially located between two adjacent negative polarity pins of the plurality of negative polarity pins. The positive polarity pin includes a first extension portion and a second extension portion. The first extension portion intersects the second extension portion.
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公开(公告)号:US12040262B2
公开(公告)日:2024-07-16
申请号:US17381931
申请日:2021-07-21
申请人: Apple Inc.
发明人: Dennis R. Pyper , Leilei Zhang , Lan H. Hoang
CPC分类号: H01L23/49822 , H01L21/481 , H01L21/4857 , H01L23/49894 , H01L23/58 , H01L21/561 , H01L23/3121 , H01L23/4985 , H01L24/16 , H01L25/105 , H01L2224/16227
摘要: Flexible modules and methods of manufacture are described. In an embodiment, a flexible module includes a flex board formed in which a passivation layer is applied in liquid form in a panel level process, followed by exposure and development. An electronic component is then mounted onto the flex board and encapsulated in a molding compound that is directly on a top surface of the passivation layer.
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公开(公告)号:US12016116B2
公开(公告)日:2024-06-18
申请号:US18208923
申请日:2023-06-13
发明人: Yong Jin Shin , Kyun Ho Kim , Uk Jae Jang , Bong Im Park
IPC分类号: H05K1/02 , G09G3/00 , H01L23/498 , H05K1/14 , H05K1/18
CPC分类号: H05K1/0268 , G09G3/006 , H01L23/49838 , H05K1/14 , H05K1/18 , G09G2330/12 , H01L23/4985 , H05K2201/049 , H05K2201/10128
摘要: A display device including: a display panel; a first substrate attached to a side of the display panel; and a second substrate attached to a side of the first substrate, wherein the display panel includes a first panel test pad and a second panel test pad, the first substrate includes a 1-1 circuit test lead overlapping and connected to the first panel test pad, a 1-2 circuit test lead overlapping and connected to the second panel test pad, a 2-1 circuit test lead overlapping and connected to the second substrate, a 1-1 test lead line connected to the 1-1 circuit test lead, a 1-2 test lead line connected to the 1-2 circuit test lead, and a first test lead line connected to the 2-1 circuit test lead, and the 1-1 test lead line and the 1-2 test lead line are connected to the first test lead line.
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公开(公告)号:US12002744B2
公开(公告)日:2024-06-04
申请号:US17356899
申请日:2021-06-24
发明人: Myong-Soo Oh , Minsung Kim , Juno Song , Heejong Shin
IPC分类号: H01L25/18 , G09G3/3241 , H01L21/48 , H01L21/66 , H01L23/498 , H01L23/544 , H10K59/131
CPC分类号: H01L23/49838 , G09G3/3241 , H01L21/4803 , H01L22/20 , H01L23/4985 , H01L23/544 , G09G2310/0243 , G09G2330/02 , H01L25/18 , H10K59/131
摘要: A film package includes a base substrate having a bottom surface that includes a first portion and a second portion that are spaced apart from each other. First pad wires are disposed on the first portion of the bottom surface of the base substrate. Second pad wires are disposed on the second portion of the bottom surface of the base substrate. A light blocking member is disposed between the first pad wires and the second pad wires.
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公开(公告)号:US11968869B2
公开(公告)日:2024-04-23
申请号:US17732500
申请日:2022-04-28
申请人: InnoLux Corporation
发明人: Ya-Wen Lin , Chien-Chih Chen , Yen-Hsi Tu , Cheng-Wei Chang , Shu-Hui Yang
IPC分类号: H10K59/18 , H01L23/498 , H01L27/15 , H10K77/10 , H10K102/00
CPC分类号: H10K59/18 , H01L23/4985 , H01L27/156 , H10K77/111 , H10K2102/311
摘要: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.
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公开(公告)号:US20240120306A1
公开(公告)日:2024-04-11
申请号:US17980571
申请日:2022-11-04
发明人: Kai-Kuang Ho , Yu-Jie Lin , Yi-Feng Hsu
IPC分类号: H01L23/00 , H01L23/498 , H01L25/065
CPC分类号: H01L24/32 , H01L23/4985 , H01L24/08 , H01L24/83 , H01L24/94 , H01L24/95 , H01L25/0657 , H01L2224/08145 , H01L2224/08238 , H01L2224/32054 , H01L2224/32225 , H01L2224/80203 , H01L2224/80895 , H01L2224/83203 , H01L2225/06524 , H01L2225/06527 , H01L2225/06568 , H01L2924/15151 , H01L2924/182
摘要: A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.
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公开(公告)号:US20240110276A1
公开(公告)日:2024-04-04
申请号:US18535530
申请日:2023-12-11
发明人: Richard C. Cope
IPC分类号: C23C14/56 , G06F3/14 , G09F9/30 , G09F9/33 , G09G3/00 , G09G3/20 , H01L23/498 , H01L25/065 , H01L25/075 , H01L31/0392 , H01L31/20 , H01L33/20 , H01L33/48
CPC分类号: C23C14/562 , G06F3/1438 , G06F3/1446 , G09F9/30 , G09F9/301 , G09F9/33 , G09G3/035 , G09G3/2088 , H01L23/4985 , H01L25/0655 , H01L25/0753 , H01L31/03923 , H01L31/206 , H01L33/20 , H01L33/48 , H01L33/483 , G09G3/20 , G09G3/32
摘要: A display includes a plurality of pixel chips, chixels, provided on a substrate. The chixels and the light emitters thereon may be shaped, sized and arranged to minimize chixel, pixel, and sub-pixel gaps and to provide a seamless look between adjacent display modules. The substrate may include light manipulators, such as filters, light converters and the like to manipulate the light emitted from light emitters of the chixels. The light manipulators may be arranged to minimize chixel gaps between adjacent chixels.
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公开(公告)号:US20240096779A1
公开(公告)日:2024-03-21
申请号:US17949142
申请日:2022-09-20
发明人: Wei-Hao CHANG
IPC分类号: H01L23/498 , H01L23/31 , H01L23/538
CPC分类号: H01L23/4985 , H01L23/3121 , H01L23/3135 , H01L23/49822 , H01L23/49838 , H01L23/5383 , H01L23/5387 , H01L24/13
摘要: A flexible package is provided. The flexible package includes a first carrier and a second carrier. The second carrier is electrically connected to the first carrier. The second carrier is at least partially embedded in the first carrier, and an electrical connection interface between the first carrier and the second carrier is within the first carrier.
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10.
公开(公告)号:US20240079311A1
公开(公告)日:2024-03-07
申请号:US18229035
申请日:2023-08-01
发明人: Seung Hyun CHO , Jeong-Kyu Ha , Jae-Min Jung
IPC分类号: H01L23/498 , B32B7/12 , B32B27/06
CPC分类号: H01L23/4985 , B32B7/12 , B32B27/06 , H01L23/49822 , H01L24/16 , H01L2224/16225
摘要: A semiconductor package includes a film substrate; a wiring layer provided on the film substrate; and a semiconductor chip provided on the wiring layer and electrically connected to the wiring layer. The film substrate includes a first layer, wherein the first layer is an insulating layer having the wiring layer thereon. The film substrate further includes a second layer, wherein the second layer is attached to a bottom of the first layer and comprises a gas. The second layer is configured to be peeled off of the first layer.
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