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    Charge storage target and method of manufacture
    4.
    发明授权
    Charge storage target and method of manufacture 失效
    充电储存目标和制造方法

    公开(公告)号：US3821092A

    公开(公告)日：1974-06-28

    申请号：US29671872

    申请日：1972-10-11

    Applicant: WESTINGHOUSE ELECTRIC CORP

    Inventor： FROBENIUS W

    IPC: H01J9/233 ,  H01J29/44 ,  H01L27/00 ,  H01L31/10 ,  C23B5/48 ,  H01J31/26 ,  H01L15/00

    CPC classification number: H01J29/44 ,  H01J9/233 ,  H01L27/00

    Abstract: A charge storage device of the type in which a target electrode provides a plurality of spatially distributed charge storage sites formed on an output side of semiconductor wafer with means associated with the storage sites for sensing and converting the charge on the storage sites into an electrical signal. Input excitation is directed onto the other or input side of the semiconductor wafer and may be in the form of electrons or light capable of generating electron-hole pairs within the semiconductor wafer which diffuse through to the storage sites. The output side of the semiconductor wafer is provided with an apertures insulating layer with a reading electron beam making contact through the apertures in the insulating coating to the spatially distributed storage sites within these apertures. This invention is directed to an improvement in the structure and the process for manufacture thereof wherein pillars of the semiconductive wafer extend from the substrate of the wafer above the insulating layer and a semiconductive region of opposite type conductivity to that of the wafer is provided in the top of the pillar and an electrical conductive contact is provided on the top of said pillar for better electron beam contact to the target. The invention is directed to this structure and the process of fabricating the electrical contact onto the top of the pillar. The process includes the spinning of a resist coating over the pillared surface of the target in such a manner to provide a desired resist pattern for the manufacturing process and thereby avoids other difficult masking process steps.

    Electroless and electrolytic copper plating
    5.
    发明授权
    Electroless and electrolytic copper plating 失效
    电镀和电镀铜镀层

    公开(公告)号：US3819497A

    公开(公告)日：1974-06-25

    申请号：US27314572

    申请日：1972-07-19

    Applicant: MACDERMID INC

    Inventor： GRUNWALD J ,  RHODENIZER H ,  SLOMINSKI L

    IPC: C23C18/18 ,  H05K3/06 ,  H05K3/10 ,  H05K3/42 ,  C23B5/48 ,  C23B5/52

    CPC classification number: H05K3/108 ,  C23C18/1653 ,  C23C18/1844 ,  H05K3/062 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2203/0392 ,  H05K2203/072 ,  H05K2203/1105

    Abstract: Copper surfaces are plated in a process comprising etching, activating, electroless and electrolytic copper deposition, and heating or baking at a temperature of about 150* to about 450*F. for about 10 min. to about 2 hours or more. Substantial improvement in the adhesion between the copper surface and the metal deposited by electroless and electrolytic plating is achieved. Processes for plating on copper-clad plastic substrates and for the manufacture of printed circuit boards are also set forth.

    Abstract translation: 铜表面以包括蚀刻，活化，无电解和电解铜沉积以及在约150°至约450°F的温度下加热或烘烤约10分钟的方法进行电镀。 至约2小时以上。 实现铜表面和通过化学镀和电解电镀沉积的金属之间的粘合力的显着改善。 还阐述了在包铜塑料基板上的电镀工艺和用于制造印刷电路板的工艺。

    Process for tantalliding and niobiding base metal compositions
    6.
    发明授权
    Process for tantalliding and niobiding base metal compositions 失效
    TANTALLIDING和NIOBIDITE基础金属组合物的方法

    公开(公告)号：US3814673A

    公开(公告)日：1974-06-04

    申请号：US18976371

    申请日：1971-10-15

    Applicant: GEN ELECTRIC

    Inventor： COOK N

    IPC: C23C18/54 ,  C25D3/66 ,  C23B5/30 ,  C23B5/48

    CPC classification number: C23C18/54 ,  C25D3/66

    Abstract: A TANTALLIDE OR NIOBIDE COATING IS FORMED ON SPECIFIED BASE METAL COMPOSITIONS BY MAKING THE BASE METAL THE CATHODE JOINED THROUGH AM EXTERNAL ELECTRICAL CIRCUIT TO A TANTAUM OR NIOBIUM ANODE IN AN ELECTRIC CELL HAVING A SPECIFIED FUSED SALT ELECTROLYTE AT A TEMPERATURE OF AT LEAST 900*C., BUT BELOW THE MLETING POINT OF THE METAL COMPOSITION. SUCH A COMBINATION IS A SELF-GENERATING CELL PRODUCING ELECTRIC BUT AN EXTERNAL E.M.F. MAY BE IMPRESSED PROVIDING THE CURRENT DENSITY DOES NOT EXCEED 10 EMPERS/CM.2. THE PROCESS IS USEFUL IN MAKING TIGHT ADHERENT COATINGS COMPOSED OF TANTALUM OR NIOBIUM AND THE BASE METAL ON THE SURFACE OF THE SUBSTRATE.

    Electrolyte and method for electroplating an indium-copper alloy and printed circuits so plated
    7.
    发明授权
    Electrolyte and method for electroplating an indium-copper alloy and printed circuits so plated 失效
    用于电镀铜 - 铜合金和印刷电路的电解质和方法

    公开(公告)号：US3812020A

    公开(公告)日：1974-05-21

    申请号：US84919369

    申请日：1969-08-11

    Applicant: ALLIED CHEM

    Inventor： MEY J

    IPC: C25D3/56 ,  H05K1/09 ,  H05K3/42 ,  C23B5/32 ,  C23B5/34 ,  C23B5/48

    CPC classification number: C25D3/56 ,  H05K1/09 ,  H05K3/423 ,  Y10S205/92

    Abstract: THIS INVENTION RELATES TO A NOVEL ELECTROPLATING BATH FOR THE ELECTRODEPOSITION OF METAL IONS FROM AN ACID SOLUTION OF SAID METAL IONS AND INDIUM IONS. THE PLATING BATHS OF THIS INVENTION PRODUCE A BRIGHT, DUCTILE, MORE REFINED GRAINED METAL COATING AND ALLOW A HIGHER LIMITING CURRENT DENSITY. PREFERABLY THE BATH IS A COPPER PLATING BATH COMPRISING A MIXTURE OF A COPPER SALTS, INDIUM SALT AND AN ACID SELECTED FROM THE GROUP CONSISTING OF SULFURIC, PHOSPHORIC, FLUOBORIC AND MIXTURES THEREOF, EACH BEING PRESENT IN AN AMOUNT WHICH UPON DISSOLUTION IN AN AQUEOUS BATH PROVIDES A COPPER CONCENTRATION FROM 5 TO 35 GRAMS PER LITER, AN INDIUM CONCENTRATION SUCH THAT THE WEIGHT RATIO OF INDIUM TO COPPER RANGES FROM 0.002 TO 4.0 AND AN ACID CONCENTRATION FROM 100 TO 700 GRAMS PER LITER. THE COPPER PLATING BATHS HAVE PARTICULAR EFFICACY IN THE COPPER PLATING OF RECESSED AREAS, SUCH AS PERFORATED SUBSTRATES, FOR USE AS PRINTED CIRCUIT BOARDS.

    Method of making insulated gate field effect transistor
    9.
    发明授权
    Method of making insulated gate field effect transistor 失效
    制造绝缘栅场效应晶体管的方法

    公开(公告)号：US3775262A

    公开(公告)日：1973-11-27

    申请号：US3775262D

    申请日：1972-02-09

    Applicant: NCR

    Inventor： HEYERDAHL N

    IPC: H01L29/78 ,  H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/00 ,  C23B5/48

    CPC classification number: H01L21/31687 ,  H01L29/00 ,  Y10S148/049 ,  Y10S148/053 ,  Y10S148/106 ,  Y10S148/118

    Abstract: The present invention relates to an insulated gate field effect transistor and method of making same. An aluminum film is evaporated on a silicon wafer. Portions of the aluminum film are masked. The unmasked portions are anodized. The unanodized portions are removed leaving the anodized insulative portions thereon. Dopant atoms are diffused into areas of the silicon wafer which are not covered by the anodized insulative layer. The anodized insulative layer acts as a diffusion mask, to form source and drain regions in the silicon wafer, and to thus delineate a gate insulator layer between the source and drain regions by the act of diffusion. A second aluminum film is evaporated over the silicon wafer. The portions of the areas of the second aluminum film over the source and drain regions, and the area of the second aluminum film over the aligned gate insulator layer are masked. The unmasked portions of the second aluminum film are anodized to delineate an aligned gate electrode over the aligned gate insulator layer and to delineate source and drain electrodes in contact with the source and drain regions. An insulated gate field effect transistor is thus formed.

    Abstract translation: 本发明涉及绝缘栅场效应晶体管及其制造方法。

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