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公开(公告)号：US20250080117A1
公开(公告)日：2025-03-06
申请号：US18240278
申请日：2023-08-30
Applicant: Texas Instruments Incorporated
Inventor： Robert Taft , Alexander Bodem , Filip Savic , Paul Kramer , Vineethraj Rajappan Nair
Abstract: An example apparatus includes: first through eighth gated inverters each having inputs and outputs; a first and second inverter each having an input and an output, the output of the first inverter coupled to the input of the second gated inverter, the output of the second inverter coupled to the input of the third gated inverter; the fifth gated inverter coupled to the input of the first gated inverter and the input of the first inverter; the sixth gated inverter coupled to the input of the second inverter and the input of the fourth gated inverter; the seventh gated inverter coupled to the output of the first gated inverter and the output of the third gated inverter; the eighth gated inverter coupled to the output of the second gated inverter and the output of the fourth gated inverter; and a bus-holder circuit between the seventh and eighth gated inverter inputs.
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公开(公告)号：US10116319B2
公开(公告)日：2018-10-30
申请号：US15911141
申请日：2018-03-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Callaghan Taft , Alexander Bodem
Abstract: A circuit including an amplifier array including an amplifier stage with M amplifiers (M≥2), connected to a resistor interpolator (interpolation order N≥2) including an input row and at least a second row, each row comprising interpolation resistors connected in series at nodes. The input row including M driven nodes connected to a respective amplifier, and connected in parallel to the second row, with at least some first-row interpolation nodes connected to corresponding second-row interpolation nodes. The resistor interpolator comprising at least one multi-row interpolation cell, with: in the input row, a driven node coupled through first and second interpolation resistors to respective adjacent first and second interpolation nodes; and in the second row, third and fourth interpolation nodes coupled through third and fourth interpolation resistors to an intermediate fifth interpolation node; and with the first and second interpolation nodes connected respectively to the third and fourth interpolation nodes.
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公开(公告)号：US20180254780A1
公开(公告)日：2018-09-06
申请号：US15911141
申请日：2018-03-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Callaghan Taft , Alexander Bodem
CPC classification number: H03M1/203 , H03F3/19 , H03F3/45475 , H03F2200/451 , H03M1/1245 , H03M1/445
Abstract: A circuit including an amplifier array including an amplifier stage with M amplifiers (M≥2), connected to a resistor interpolator (interpolation order N≥2) including an input row and at least a second row, each row comprising interpolation resistors connected in series at nodes. The input row including M driven nodes connected to a respective amplifier, and connected in parallel to the second row, with at least some first-row interpolation nodes connected to corresponding second-row interpolation nodes. The resistor interpolator comprising at least one multi-row interpolation cell, with: in the input row, a driven node coupled through first and second interpolation resistors to respective adjacent first and second interpolation nodes; and in the second row, third and fourth interpolation nodes coupled through third and fourth interpolation resistors to an intermediate fifth interpolation node; and with the first and second interpolation nodes connected respectively to the third and fourth interpolation nodes.
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