-
1.发明授权公开(公告)号：US06972706B2
公开(公告)日：2005-12-06
申请号：US10669590
申请日：2003-09-23
Applicant: Walter Jan Maria Snoeijs
Inventor： Walter Jan Maria Snoeijs
CPC classification number: G11C27/026 , G11C11/56 , G11C27/028 , H03M1/445
Abstract: A current folding cell has current inputs and current outputs. Input currents are transferred from one current path to another and finally leading to the current outputs to establish a continuous folding characteristic. The signal current through one of the current paths often does not need to be substantially zero around the folding point in the folding characteristic. Comparator outputs in the cell provide digital outputs corresponding to the currents at the current inputs. An A/D converter can be constructed utilizing such current folding circuit cells in cascade and/or in parallel. The well-determined relationship between folder outputs can be used in a feedback loop to reduce or eliminate mismatch contributions. A mixer can be constructed using such current folding cells.
Abstract translation: 电流折叠电池具有电流输入和电流输出。 输入电流从一个电流路径转移到另一个电流路径，最后导致电流输出以建立连续的折叠特性。 通过一条电流路径的信号电流在折叠特性中的折叠点周围通常不需要基本为零。 单元格中的比较器输出提供与当前输入电流相对应的数字输出。 可以利用级联和/或并联的这种电流折叠电路单元来构造A / D转换器。 文件夹输出之间确定的关系可以用在反馈回路中，以减少或消除失配贡献。 可以使用这样的当前折叠单元来构造混合器。
-
2.发明申请公开(公告)号：US20030132867A1
公开(公告)日：2003-07-17
申请号：US10046871
申请日：2002-01-15
Inventor： Kenneth A. Ostrom , Laura L. Carpenter
IPC: H03M001/10
CPC classification number: H03M1/109 , H03M1/1061 , H03M1/445
Abstract: An auto-calibration technique for optimizing the transfer function of analog-to-digital converters. The technique can be applied to analog-to-digital converter (ADC) architectures employing a cascade of n-stages to form a composite n-bit ADC transfer function. The technique utilizes evaluation of the probability density function of individual bits to determine error sign, minimize error magnitude and assure calibration convergence.
Abstract translation: 一种用于优化模数转换器传递函数的自动校准技术。 该技术可以应用于采用级联n级的模数转换器（ADC）架构，以形成复合n位ADC传递函数。 该技术利用单个位的概率密度函数的评估来确定误差符号，最小化误差幅度并确保校准收敛。
-
公开(公告)号：US20030058149A1
公开(公告)日：2003-03-27
申请号：US10201590
申请日：2002-07-22
Applicant: THE INDIAN INSTITUTE OF TECHNOLOGY (IItd)
Inventor： Jayadeva
IPC: H03M001/12 , H03M001/34
Abstract: The invention relates to an analog to digital converter computing all the bits in parallel or sequentially, without using decoding logic having an analog input and a digital output, wherein given the analog signal x, each bit can be computed by applying a formula containing a non linear periodic function which may be sine shaped or pulse shaped.
-
4.发明授权
公开(公告)号：US5608402A
公开(公告)日：1997-03-04
申请号：US410227
申请日：1995-03-24
Applicant: Robert J. Distinti
Inventor： Robert J. Distinti
Abstract: An Operational Analog to Digital (SYMAD) Convertor cell for converting an analog signal into a discrete binary code. An analog signal is processed by sample and hold circuitry and then compared to a reference voltage by a comparator. The comparator output is the converted digital output. This output is coupled back to the control input of an analog switch which selects either the reference voltage or a predetermined potential, typically zero volts, to couple to an inverting input of an operational amplifier. The analog signal input is also coupled to the non-inverting input of the operational amplifier. The operational amplifier is configured as a differential amplifier with a gain of two. If the digital output of the comparator is a logic 1, then the operational amplifier output is two times the difference between the analog signal and the reference voltage. If the digital output of the comparator is a logic 0, then the output of the operational amplifier is two times the analog signal. As many SYMAD cells as necessary may be provided to obtain a desired resolution.
Abstract translation: 操作模数（SYMAD）转换单元，用于将模拟信号转换为离散二进制码。 模拟信号由采样和保持电路处理，然后通过比较器与参考电压进行比较。 比较器输出是转换的数字输出。 该输出耦合回模拟开关的控制输入，模拟开关选择参考电压或预定电位（通常为零伏特）耦合到运算放大器的反相输入端。 模拟信号输入也耦合到运算放大器的非反相输入端。 运算放大器配置为增益为2的差分放大器。 如果比较器的数字输出为逻辑1，则运算放大器输出是模拟信号与参考电压之差的两倍。 如果比较器的数字输出为逻辑0，则运算放大器的输出为模拟信号的两倍。 可以提供必要的许多SYMAD电池以获得期望的分辨率。
-
5.发明授权
公开(公告)号：US5550492A
公开(公告)日：1996-08-27
申请号：US347910
申请日：1994-12-01
Applicant: Frank Murden
Inventor： Frank Murden
CPC classification number: H03F3/45596 , H03F3/26 , H03F3/45085 , H03M1/445 , H03F2203/45612
Abstract: A differential amplifier operating as a magnitude amplifier may be used in a serial-type A/D converter. The differential amplifier uses complementary differential emitter pairs for folding and aligning a differential input signal. The differential input signal has a first signal and a second signal each of which is fed to one of two input circuits. One input circuit includes a bipolar npn transistor and a current sink and the other includes a bipolar pnp transistor and a current source. The outputs of the input npn transistors feed a differential pair of output pnp transistors. The emitters of the output pnp transistors are coupled, with the signal on the emitters following the lower of the differential input signals. The outputs of the input pnp transistors feed a differential pair of output npn transistors. The emitters of the output npn transistors also are coupled, with the signal on the emitters following the inputs in a predetermined manner. The results are folded signals at the outputs of the output transistors that are aligned by offset circuits.
Abstract translation: 作为幅度放大器工作的差分放大器可用于串行型A / D转换器。 差分放大器使用互补差分发射器对来折叠和对准差分输入信号。 差分输入信号具有第一信号和第二信号，每个信号被馈送到两个输入电路之一。 一个输入电路包括双极性npn晶体管和电流吸收器，另一个包括双极pnp晶体管和电流源。 输入npn晶体管的输出馈送输出pnp晶体管的差分对。 输出pnp晶体管的发射极被耦合，发射极上的信号跟随差分输入信号的较低者。 输入pnp晶体管的输出馈送差分输出npn晶体管对。 输出npn晶体管的发射极也被耦合，发射器上的信号以预定的方式跟随输入。 结果是在由偏移电路对准的输出晶体管的输出处的折叠信号。
-
Patent Agency Ranking
公开(公告)号：US5404143A
公开(公告)日：1995-04-04
申请号：US45815
申请日：1993-04-08
Applicant: Robert J. Distinti
Inventor： Robert J. Distinti
IPC: G06N3/063 , G11C27/02 , H03M1/02 , H03M1/38 , H03M1/40 , H03M1/42 , H03M1/44 , H03M1/72 , H03M1/34
CPC classification number: H03M1/38 , G06N3/063 , G11C27/026 , H03M1/02 , H03M1/42 , H03M1/72 , H03M1/40 , H03M1/44 , H03M1/445
Abstract: An n-bit analog processing circuit constructed with network swappers has n stages and an input port for inputting an analog signal to be processed. Each of the n stages includes first and second reference input ports, at least one swappable network having first and second terminals, and a switching element that is responsive to a digital input signal for varying a connectivity of the first and second terminals with respect to the first and second reference input ports. Each of the n networks has a primary electrical characteristic that is binarily weighted with respect to others of the networks. The primary electrical characteristic may be resistance, capacitance, capacitive reactance, inductance, inductive reactance, voltage potential, gain, transconductance, superconductance, time delay, permeability, electrical or optical conductor length, and/or winding turns. A characteristic of an analog signal appearing at an output port is a function of an analog signal applied between the first and second reference input ports of a most significant stage, and is also a function of an n-bit digital signal (binary or Gray code) that is applied to the n-stages.
Abstract translation: 由网络交换器构成的n位模拟处理电路具有n个级和用于输入要处理的模拟信号的输入端口。 n个级中的每一个包括第一和第二参考输入端口，至少一个具有第一和第二端子的可交换网络，以及响应于数字输入信号的开关元件，用于改变第一和第二端子相对于 第一和第二参考输入端口。 n个网络中的每一个具有相对于网络中的其他网络二次加权的主要电气特征。 主要电气特性可以是电阻，电容，电抗，电感，感抗，电压电位，增益，跨导，超导，时间延迟，磁导率，电或光导体长度和/或绕组匝数。 出现在输出端口的模拟信号的特征是施加在最重要级的第一和第二参考输入端口之间的模拟信号的函数，并且还是n位数字信号（二进制或格雷码 ）应用于n阶段。
-
公开(公告)号：US3495233A
公开(公告)日：1970-02-10
申请号：US3495233D
申请日：1966-12-28
Applicant: BELL TELEPHONE LABOR INC
Inventor： SAARI VEIKKO R
CPC classification number: H03M1/445
-
公开(公告)号：US09356616B1
公开(公告)日：2016-05-31
申请号：US14816387
申请日：2015-08-03
Applicant: Broadcom Corporation
Inventor： Hui Pan , Xin Jin , Chia-Jen Hsu
Abstract: A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC) may sample an input signal, successively approximate the sampled signal with a shrinking sub-range containing the signal, and output coarse digital codes corresponding to the sub-range. A sub-ranging stage may continue quantization over the sub-range by sampling and interpolating between a pair of zero crossing signals that bound the sub-range. The zero crossing signals may be taken from the SAR preamp output. The sub-ranging process may be pipelined recursively in multiple stages to increase throughput and efficiency.
Abstract translation: 一个多位每周期逐次逼近寄存器（SAR）模数转换器（ADC）可以对输入信号进行采样，以包含信号的收缩子范围连续近似采样信号，并输出对应于 子范围 子范围级可以通过在绑定子范围的一对过零信号之间进行采样和内插来在子范围上继续量化。 过零信号可以取自SAR前置放大器输出。 子范围过程可以在多个阶段递归流水线以增加吞吐量和效率。
-
9.发明授权公开(公告)号：US07737774B2
公开(公告)日：2010-06-15
申请号：US12097722
申请日：2006-12-12
Applicant: François Bore , Sandrine Bruel
Inventor： François Bore , Sandrine Bruel
IPC: H03F1/02
CPC classification number: H03F3/45748 , H03F3/456 , H03F2203/45212 , H03F2203/45352 , H03F2203/45482 , H03F2203/45504 , H03F2203/45512 , H03F2203/45514 , H03M1/445
Abstract: The invention relates to analog integrated electronic circuits using differential pairs. The proposal is for a method of automatic correction of offset voltage. The inputs (V1, V2) of the differential circuit are short circuited during a calibration phase distinct from the normal usage phase. A capacitor is charged through the difference of the output currents of the branches of the differential pair in this phase. The voltage at the terminals of the capacitor is compared with at least one threshold. During the normal usage phase following the calibration phase, the result of the comparison is kept in memory. In the normal usage phase, a correction is applied depending on the result kept in memory to a current source of a follower stage upstream of the differential pair.
Abstract translation: 本发明涉及使用差分对的模拟集成电子电路。 该建议是针对偏移电压进行自动校正的方法。 在与正常使用阶段不同的校准阶段，差分电路的输入（V1，V2）短路。 在该阶段，通过差分对的分支的输出电流的差异对电容器进行充电。 将电容器端子处的电压与至少一个阈值进行比较。 在校准阶段之后的正常使用阶段，将比较结果保存在存储器中。 在正常使用阶段，根据保存在存储器中的结果对差分对上游的跟随器级的电流源进行校正。
-
10.发明申请公开(公告)号：US20090224805A1
公开(公告)日：2009-09-10
申请号：US12097722
申请日：2006-12-12
Applicant: Francois Bore , Sandrine Bruel
Inventor： Francois Bore , Sandrine Bruel
IPC: H03K5/22
CPC classification number: H03F3/45748 , H03F3/456 , H03F2203/45212 , H03F2203/45352 , H03F2203/45482 , H03F2203/45504 , H03F2203/45512 , H03F2203/45514 , H03M1/445
Abstract: The invention relates to analog integrated electronic circuits using differential pairs. The proposal is for a method of automatic correction of offset voltage. The inputs (V1, V2) of the differential circuit are short circuited during a calibration phase distinct from the normal usage phase. A capacitor is charged through the difference of the output currents of the branches of the differential pair in this phase. The voltage at the terminals of the capacitor is compared with at least one threshold. During the normal usage phase following the calibration phase, the result of the comparison is kept in memory. In the normal usage phase, a correction is applied depending on the result kept in memory to a current source of a follower stage upstream of the differential pair.
Abstract translation: 本发明涉及使用差分对的模拟集成电子电路。 该建议是针对偏移电压进行自动校正的方法。 在与正常使用阶段不同的校准阶段，差分电路的输入（V1，V2）短路。 在该阶段，通过差分对的分支的输出电流的差异对电容器进行充电。 将电容器端子处的电压与至少一个阈值进行比较。 在校准阶段之后的正常使用阶段，将比较结果保存在存储器中。 在正常使用阶段，根据保存在存储器中的结果对差分对上游的跟随器级的电流源进行校正。
-
-
-
-
-
-
-
-
-
Search Results
47
records
(took 0.035 seconds)
