公开(公告)号：US11803455B2

公开(公告)日：2023-10-31

申请号：US18175607

申请日：2023-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

CPC classification number: G06F11/273 ,  G06F11/26 ,  G06F11/3024 ,  G06F11/3089 ,  G06F11/348 ,  G06F11/3636 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/3664

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US20230205656A1

公开(公告)日：2023-06-29

申请号：US18175607

申请日：2023-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

CPC classification number: G06F11/273 ,  G06F11/3636 ,  G06F11/3664 ,  G06F11/3648 ,  G06F11/348 ,  G06F11/3656 ,  G06F11/3024 ,  G06F11/3089 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US10929101B2

公开(公告)日：2021-02-23

申请号：US16056115

申请日：2018-08-06

Applicant: Texas Instruments Incorporated

Inventor： Christian Wiencke ,  Armin Stingl

IPC: G06F7/44 ,  G06F7/53 ,  G06F7/42

Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.

公开(公告)号：US11132203B2

公开(公告)日：2021-09-28

申请号：US14459416

申请日：2014-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Armin Stingl ,  Jeroen Vliegen

IPC: G06F9/38

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.

公开(公告)号：US10891207B2

公开(公告)日：2021-01-12

申请号：US16102193

申请日：2018-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US10049025B2

公开(公告)日：2018-08-14

申请号：US15200900

申请日：2016-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US11868780B2

公开(公告)日：2024-01-09

申请号：US17412491

申请日：2021-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Armin Stingl ,  Jeroen Vliegen

IPC: G06F9/22 ,  G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3877

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.

公开(公告)号：US11593241B2

公开(公告)日：2023-02-28

申请号：US17146584

申请日：2021-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US20210382721A1

公开(公告)日：2021-12-09

申请号：US17412491

申请日：2021-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Armin Stingl ,  Jeroen Vliegen

IPC: G06F9/38

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.

公开(公告)号：US20210133065A1

公开(公告)日：2021-05-06

申请号：US17146584

申请日：2021-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.