公开(公告)号：US11132203B2

公开(公告)日：2021-09-28

申请号：US14459416

申请日：2014-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Armin Stingl ,  Jeroen Vliegen

IPC: G06F9/38

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.

公开(公告)号：US10891207B2

公开(公告)日：2021-01-12

申请号：US16102193

申请日：2018-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US10740105B2

公开(公告)日：2020-08-11

申请号：US14245667

申请日：2014-04-04

Applicant: Texas Instruments Incorporated

Inventor： Christian Wiencke

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

Abstract: A processor includes an execution unit and a subroutine cache. The execution unit is configured to execute instructions. The subroutine cache us configured to provide instructions of a subroutine to the execution unit for execution. The subroutine cache includes subroutine instruction storage, a subroutine address register, and subroutine cache control logic. The subroutine control logic is configured to: identify a subroutine call instruction provided to the execution unit; determine whether an instruction of a subroutine invoked by the subroutine call instruction is stored in the subroutine instruction storage by evaluating a subroutine validity indicator that indicates whether at least a portion of the subroutine is stored in the subroutine instruction storage; and provide the instruction of the subroutine to the execution unit based on the subroutine validity indicator indicating that at least a portion of the subroutine is stored in the subroutine instruction storage.

公开(公告)号：US10049025B2

公开(公告)日：2018-08-14

申请号：US15200900

申请日：2016-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US20140136588A1

公开(公告)日：2014-05-15

申请号：US14155806

申请日：2014-01-15

Applicant: Texas Instruments Incorporated

Inventor： Christian Wiencke

IPC: G06F7/523

CPC classification number: G06F7/523 ,  G06F7/5306 ,  G06F2207/382

Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na−1 multiplied with the second operand bits 0 to nb−2, selectively inverting the single bit products of the signed second operand bits 0 to na−2 multiplied with the signed second operand bit nb−1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb−1, na−1 and na+nb−1 for receiving a final product.

Abstract translation: 用于将有符号的第一操作数na位和带符号的第二操作数nb位相乘的方法和装置，其中na和nb是不同的正整数，该方法包括从签名的第一操作数生成单位对的单位产物和单符号 从具有逻辑“和”功能的带符号的第二操作数开始，产生无效的单位乘积，对于有符号的第一操作数和有符号的第二操作数有选择地反相，第一操作数位na-1的单位乘积与第二操作数位相乘 0到nb-2，在反转步骤之后，根据它们各自的顺序反相添加单个位产物，选择性地将符号的第二操作数位0到na-2的单个比特乘积与有符号的第二操作数位nb-1相乘 用于产生中间产品，并且在位置nb-1，na-1和na + nb-1处添加用于接收最终产品的“1”比特值。

公开(公告)号：US11868780B2

公开(公告)日：2024-01-09

申请号：US17412491

申请日：2021-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Armin Stingl ,  Jeroen Vliegen

IPC: G06F9/22 ,  G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3877

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.

公开(公告)号：US11593241B2

公开(公告)日：2023-02-28

申请号：US17146584

申请日：2021-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US11513804B2

公开(公告)日：2022-11-29

申请号：US17029299

申请日：2020-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Markus Koesler ,  Johann Zipperer ,  Christian Wiencke ,  Wolfgang Lutsch

IPC: G06F11/36 ,  G06F9/38 ,  G06F11/267 ,  G06F9/30

Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

公开(公告)号：US20210382721A1

公开(公告)日：2021-12-09

申请号：US17412491

申请日：2021-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Armin Stingl ,  Jeroen Vliegen

IPC: G06F9/38

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.

公开(公告)号：US09372665B2

公开(公告)日：2016-06-21

申请号：US14155806

申请日：2014-01-15

Applicant: Texas Instruments Incorporated

Inventor： Christian Wiencke

IPC: G06F7/53 ,  G06F7/523

CPC classification number: G06F7/523 ,  G06F7/5306 ,  G06F2207/382

Abstract: Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na−1 multiplied with the second operand bits 0 to nb−2, selectively inverting the single bit products of the signed second operand bits 0 to na−2 multiplied with the signed second operand bit nb−1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb−1, na−1 and na+nb−1 for receiving a final product.

Abstract translation: 用于将有符号的第一操作数na位和带符号的第二操作数nb位相乘的方法和装置，其中na和nb是不同的正整数，该方法包括从签名的第一操作数生成单位对的单位产物和单符号 从具有逻辑“和”功能的带符号的第二操作数开始，产生无效的单位乘积，对于有符号的第一操作数和有符号的第二操作数有选择地反相，第一操作数位na-1的单位乘积与第二操作数位相乘 0到nb-2，在反转步骤之后，根据它们各自的顺序反相添加单个位产物，选择性地将符号的第二操作数位0到na-2的单个比特乘积与有符号的第二操作数位nb-1相乘 用于产生中间产品，并且在位置nb-1，na-1和na + nb-1处添加用于接收最终产品的“1”比特值。