BUTTERFLY NETWORK ON LOAD DATA RETURN
    5.
    发明申请

    公开(公告)号:US20190020360A1

    公开(公告)日:2019-01-17

    申请号:US15651055

    申请日:2017-07-17

    Abstract: A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits.

    SUPERIMPOSING BUTTERFLY NETWORK CONTROLS FOR PATTERN COMBINATIONS

    公开(公告)号:US20180341616A1

    公开(公告)日:2018-11-29

    申请号:US15602235

    申请日:2017-05-23

    Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

    BUTTERFLY NETWORK ON LOAD DATA RETURN
    8.
    发明公开

    公开(公告)号:US20240063827A1

    公开(公告)日:2024-02-22

    申请号:US18498196

    申请日:2023-10-31

    CPC classification number: H03M13/6561 G06F9/38 H03M13/2789 H03M13/276

    Abstract: A system, method, and device are shown that are operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network by selectably switching bit positions of the input data stream. In some examples, a device includes a first circuit configured to selectably switch bit positions of a first subset of the data stream with a second subset of the data stream and a second circuit configured to: selectably switch bit positions of a first subset of the first subset of the data stream with a second subset of the first subset of the data stream, and selectably switch bit positions of a first subset of the second subset of the data stream with a second subset of the second subset of the data stream.

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