公开(公告)号：US10516401B2

公开(公告)日：2019-12-24

申请号：US16214179

申请日：2018-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayawardan Janardhanan ,  Eric Paul Lindgren ,  Henry Yao

IPC: H03L7/081 ,  H03L7/10

Abstract: A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clock. A pseudo random binary sequence generator generates a pseudo random binary bit sequence to be used to vary the amount of time delay added by the first delay line to the third clock.

公开(公告)号：US10516402B2

公开(公告)日：2019-12-24

申请号：US16232893

申请日：2018-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eric Paul Lindgren ,  Arvind Sridhar ,  Jayawardan Janardhanan

IPC: H03L7/085

Abstract: A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.