公开(公告)号：US20200058570A1

公开(公告)日：2020-02-20

申请号：US16540943

申请日：2019-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kengo Aoya ,  Masamitsu Matsuura ,  Takeshi Onogami ,  Hideaki Matsunaga

IPC: H01L23/31 ,  H01L23/16 ,  H01L23/498 ,  H01L23/053 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.

公开(公告)号：US12154861B2

公开(公告)日：2024-11-26

申请号：US16669666

申请日：2019-10-31

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

公开(公告)号：US20230137762A1

公开(公告)日：2023-05-04

申请号：US17515234

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya ,  Hideaki Matsunaga ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00

Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.

公开(公告)号：US20210134729A1

公开(公告)日：2021-05-06

申请号：US16669666

申请日：2019-10-31

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

公开(公告)号：US20250087591A1

公开(公告)日：2025-03-13

申请号：US18960733

申请日：2024-11-26

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

公开(公告)号：US11942384B2

公开(公告)日：2024-03-26

申请号：US17515234

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya ,  Hideaki Matsunaga ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/4952 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16245 ,  H01L2224/48245

Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.