公开(公告)号：US20150008566A1

公开(公告)日：2015-01-08

申请号：US14320803

申请日：2014-07-01

Applicant: Texas Instruments Incorporated

Inventor： Mark A. Gerber ,  Mutsumi Masumoto ,  Kenji Masumoto ,  Anindya Poddar ,  Kengo Aoya ,  Masamitsu Matsuura ,  Takeshi Onogami

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape (292); attaching semiconductor chips—coated with a polymer layer having windows for chip terminals —face-down onto the tape (293); laminating low CTE insulating material to fill gaps between chips and grid (294); turning over assembly to place carrier under backside of chips and lamination and to remove tape (295); plasma-cleaning assembly front side, sputtering uniform metal layer across assembly (296); optionally plating metal layer (297); and patterning sputtered layer to form rerouting traces and extended contact pads for assembly (298).

Abstract translation: 一种以面板格式制造封装半导体器件的方法; 将具有开口的面板尺寸的金属网格放置在胶带（292）上; 将具有用于芯片端子的具有窗口的聚合物层的半导体芯片附接到带（293）上; 层压低CTE绝缘材料以填充芯片和网格之间的间隙（294）; 翻转组件以将载体放置在芯片的背面和层压之下并去除带（295）; 等离子体清洁组件正面，横跨组装的溅射均匀金属层（296）; 可选地镀金属层（297）; 并且图案化溅射层以形成重新布线迹线和用于组装的扩展接触垫（298）。

公开(公告)号：US20150147845A1

公开(公告)日：2015-05-28

申请号：US14552548

申请日：2014-11-25

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mark Allen Gerber ,  Mutsumi Masumoto ,  Masamitsu Matsuura ,  Kengo Aoya ,  Takeshi Onogami

IPC: H01L25/00 ,  H01L21/304 ,  H01L21/683 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L21/561 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.

Abstract translation: 本发明的实施例提供了一种用于形成双面嵌入式模具系统的方法。 该方法从起始材料开始，包括顶表面和底表面，多个通孔，多个电镀金属柱，冲压垫和加强件。 将表面平坦化以暴露所包含的金属，其不是从管芯附着垫DAP区域选择性地蚀刻以形成空腔。 通过使用光刻胶图案和电镀创建一个加强筋。 涂抹胶带。 附上一个模具 层压和研磨。 去除胶带。 形式重新分配层RDL和焊接掩模。 安装表面贴装器件。

公开(公告)号：US20200058570A1

公开(公告)日：2020-02-20

申请号：US16540943

申请日：2019-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kengo Aoya ,  Masamitsu Matsuura ,  Takeshi Onogami ,  Hideaki Matsunaga

IPC: H01L23/31 ,  H01L23/16 ,  H01L23/498 ,  H01L23/053 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.

公开(公告)号：US20160240392A1

公开(公告)日：2016-08-18

申请号：US15137114

申请日：2016-04-25

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mark Allen Gerber ,  Mutsumi Masumoto ,  Masamitsu Matsuura ,  Kengo Aoya ,  Takeshi Onogami

IPC: H01L21/56 ,  H01L21/48

CPC classification number: H01L21/561 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.