公开(公告)号：US20240363606A1

公开(公告)日：2024-10-31

申请号：US18768925

申请日：2024-07-10

Applicant: ROHM CO., LTD.

Inventor： Yoshizo OSUMI ,  Tsunehisa ONO

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/64

CPC classification number: H01L25/16 ,  H01L23/3107 ,  H01L23/49558 ,  H01L23/645 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48195 ,  H01L2224/48245 ,  H01L2924/1426 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: The semiconductor device includes an insulating element, a conductive member, a sealing resin, and a discharge path. The conductive member includes a first terminal and a second terminal that are electrically connected to the insulating element. The sealing resin includes a resin first surface and a resin second surface. The first terminal protrudes from the resin first surface. The resin second surface faces away from the resin first surface in a first direction perpendicular to a thickness direction of the insulating element. The second terminal protrudes from the resin second surface. The discharge path is a conductive path between the first terminal and the second terminal, and is electrically conductive at a voltage lower than a dielectric withstand voltage of the insulating element.

公开(公告)号：US12131983B2

公开(公告)日：2024-10-29

申请号：US17697804

申请日：2022-03-17

Applicant: ROHM CO., LTD.

Inventor： Katsutoki Shirai

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49565 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/4801 ,  H01L2224/48245 ,  H01L2224/4845 ,  H01L2224/48455 ,  H01L2224/4903 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2924/186

Abstract: A semiconductor device, includes: a semiconductor element having element main surface and element back surface spaced apart from each other in thickness direction and including a plurality of main surface electrodes arranged on the element main surface; a die pad having a die pad main surface where the semiconductor element is mounted; a plurality of leads including at least one first lead arranged on one side in first direction orthogonal to the thickness direction with respect to the die pad, and arranged around the die pad when viewed in the thickness direction; a plurality of connecting members including a first connecting member bonded to the at least one first lead, and configured to electrically connect the main surface electrodes and the leads; and a resin member configured to seal the semiconductor element, a part of the die pad, parts of the leads, and the connecting members.

公开(公告)号：US20240290694A1

公开(公告)日：2024-08-29

申请号：US18651155

申请日：2024-04-30

Applicant: Rohm Co., Ltd.

Inventor： Ryotaro KAKIZAKI

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/4842 ,  H01L23/3121 ,  H01L23/49555 ,  H01L24/29 ,  H01L24/32 ,  H01L24/06 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/46 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/49052 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor device includes a semiconductor element, a first lead including a die pad portion and a first terminal portion, and a sealing resin. A first-lead reverse surface is exposed from a second resin surface. The first terminal portion includes a first section joined to the die pad portion, a second section located on a first side in a z direction with respect to the first section and used for mounting, and a third section between the first section and the second section.

公开(公告)号：US12068235B2

公开(公告)日：2024-08-20

申请号：US17596235

申请日：2020-06-10

Applicant: ROHM CO., LTD.

Inventor： Masaaki Matsuo ,  Yoshihisa Tsukamoto

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L25/07

CPC classification number: H01L23/49844 ,  H01L23/481 ,  H01L23/49811 ,  H01L25/072 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/30107

Abstract: Semiconductor device A1 includes: semiconductor element 1 turning on and off connection between drain electrode 11 and source electrode 12; semiconductor element 2 turning on and off connection between drain electrode 21 and source electrode 22; metal component 31 with semiconductor element 1 mounted; metal component 32 with semiconductor element 2 mounted; and conductive substrate 4 including wiring layers 411, 412 with insulating layer 421 between them. Wiring layer 411 includes power terminal section 401 connected to drain electrode 11. Wiring layer 412 includes power terminal section 402 connected to source electrode 22. Power terminal sections 401, 402 and insulating layer 421 overlap with each other as viewed in z direction. Conductive substrate 4 surrounds semiconductor elements 1, 2 as viewed in z direction, while overlapping with a portion between metal components 31, 32 as viewed in z direction.

公开(公告)号：US20240274570A1

公开(公告)日：2024-08-15

申请号：US18648632

申请日：2024-04-29

Applicant: Texas Instruments Incorporated

Inventor： Chien-Chang Li ,  Hung-Yu Chou ,  Sheng-Wen Huang ,  Zi-Xian Zhan ,  Byron Lovell Williams

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L24/48 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/85 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/85051 ,  H01L2224/85205

Abstract: An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.

公开(公告)号：US20240266263A1

公开(公告)日：2024-08-08

申请号：US18469516

申请日：2023-09-18

Applicant: Mitsubishi Electric Corporation

Inventor： Mamoru TOGAMI ,  Kosuke YAMAGUCHI ,  Shogo SHIBATA ,  Kazufumi OKI

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/48245

Abstract: According to the present disclosure, a semiconductor apparatus comprises a plurality of integrated circuits, an IC frame on which the plurality of integrated circuits are mounted, and a sealing material. The IC frame comprises a first protrusion extending in a longitudinal direction of the IC frame, a second protrusion positioned on the opposite side to the first protrusion in the IC frame and extending in an opposite direction to the first protrusion, and a third protrusion extending in a direction perpendicular to the longitudinal direction of the IC frame and incorporated in the sealing material.

公开(公告)号：US12040302B2

公开(公告)日：2024-07-16

申请号：US17523119

申请日：2021-11-10

Applicant: Infineon Technologies Austria AG

Inventor： Hyeongnam Kim ,  Mohamed Imam

IPC: H01L21/78 ,  H01L21/66 ,  H01L23/00 ,  H01L29/423

CPC classification number: H01L24/40 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/84 ,  H01L24/85 ,  H01L29/4238 ,  H01L2224/40245 ,  H01L2224/48245 ,  H01L2224/73221 ,  H01L2924/13064 ,  H01L2924/37001

Abstract: A transistor package having four terminals includes a semiconductor transistor chip and a semiconductor diode chip. The semiconductor transistor chip includes a control electrode and a first load electrode on a first surface and a second load electrode on a second surface opposite the first surface. The semiconductor diode chip includes a first diode electrode on a first surface and a second diode electrode on a second surface opposite the first surface. The transistor package includes a first terminal electrically connected to the control electrode, a second terminal electrically connected to the first diode electrode, a third terminal electrically connected to the first load electrode and a fourth terminal electrically connected to the second load electrode. At least the first terminal, the second terminal and the third terminal protrude from one side of transistor package. The first terminal is arranged between the second terminal and the third terminal.

公开(公告)号：US20240234231A1

公开(公告)日：2024-07-11

申请号：US18617517

申请日：2024-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  Qiao CHEN

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/315 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/19104

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

公开(公告)号：US20240213178A1

公开(公告)日：2024-06-27

申请号：US18595905

申请日：2024-03-05

Applicant: Texas Instruments Incorporated

Inventor： Tomoko NOGUCHI ,  Mutsumi MASUMOTO ,  Kengo AOYA ,  Masamitsu MATSUURA

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48245

Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.

公开(公告)号：US20240203930A1

公开(公告)日：2024-06-20

申请号：US18380053

申请日：2023-10-13

Applicant: Adeia Semiconductor Solutions LLC

Inventor： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L27/146

CPC classification number: H01L24/48 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49811 ,  H01L24/18 ,  H01L24/73 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14625 ,  H01L21/56 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1713 ,  H01L2224/17179 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48464 ,  H01L2224/49105 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01049 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.