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公开(公告)号:US20240290676A1
公开(公告)日:2024-08-29
申请号:US18174039
申请日:2023-02-24
Applicant: Texas Instruments Incorporated
Inventor: Masamitsu Matsuura , Makoto Shibuya , Daiki Komatsu , Kengo Aoya
IPC: H01L23/31 , H01L21/56 , H01L23/367 , H01L23/495 , H01L23/498 , H01L25/16
CPC classification number: H01L23/3135 , H01L21/56 , H01L23/367 , H01L23/49555 , H01L23/49562 , H01L23/49811 , H01L25/16 , H01L23/49589 , H01L23/49833 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/06051 , H01L2224/2919 , H01L2224/32227 , H01L2224/32245 , H01L2224/40137 , H01L2224/40475 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45664 , H01L2224/48091 , H01L2224/48106 , H01L2224/48108 , H01L2224/48175 , H01L2224/48229 , H01L2224/49113 , H01L2224/49175 , H01L2224/73221 , H01L2224/73253 , H01L2224/73265 , H01L2924/0665 , H01L2924/10253 , H01L2924/10272 , H01L2924/1033 , H01L2924/13091
Abstract: A microelectronic device includes one or more electronic components attached to a package substrate which has an exposed surface to provide an area for mounting a heatsink. The microelectronic device includes one or more leads that are electrically connected to the electronic component. The lead extends away from the exposed surface of the package substrate. The microelectronic device includes a shielding dielectric material that laterally surrounds the lead and extends over the lead between the lead and the exposed surface of the package substrate. An electronic system includes the microelectronic device and a circuit board electrically connected to the lead. The electronic system also includes a heatsink attached to the exposed surface of the package substrate.
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公开(公告)号:US20230068748A1
公开(公告)日:2023-03-02
申请号:US17462067
申请日:2021-08-31
Applicant: Texas Instruments Incorporated
Inventor: Masamitsu Matsuura
IPC: H01L23/495 , H01L23/482
Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for receiving a semiconductor die, and having conductive leads spaced from the die pad; a semiconductor die mounted on the die pad, the semiconductor die having bond pads on an active surface configured for making electrical connections; electrical connections coupling the bond pads of the semiconductor die to the conductive leads; mold compound covering a portion of the package substrate, the semiconductor die, and the electrical connections, with the leads extending through the mold compound and having end portions exposed from the mold compound; and the leads having a first portion with a first width and extending with the first width from the mold compound to a second portion having a second width that greater than the first width.
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公开(公告)号:US20200058570A1
公开(公告)日:2020-02-20
申请号:US16540943
申请日:2019-08-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Kengo Aoya , Masamitsu Matsuura , Takeshi Onogami , Hideaki Matsunaga
IPC: H01L23/31 , H01L23/16 , H01L23/498 , H01L23/053 , H01L21/56 , H01L21/78 , H01L23/00
Abstract: A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.
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公开(公告)号:US20250140626A1
公开(公告)日:2025-05-01
申请号:US18495837
申请日:2023-10-27
Applicant: Texas Instruments Incorporated
Inventor: Masamitsu Matsuura , Daiki Komatsu , Kengo Aoya
Abstract: An electronic device includes a package structure having opposite first and second sides, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, the first and second sides spaced along a third direction orthogonal to the first and second directions, and an opening extending into the first side along the third direction, a first semiconductor die having a first side exposed in the opening of the package structure and an opposite second side partially enclosed by the package structure, and a second semiconductor die electrically connected to the first semiconductor die, the second semiconductor die enclosed by the package structure and laterally spaced apart from the first semiconductor die.
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公开(公告)号:US12272626B2
公开(公告)日:2025-04-08
申请号:US17683074
申请日:2022-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Makoto Shibuya , Masamitsu Matsuura , Kengo Aoya , Anindya Poddar
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31
Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.
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公开(公告)号:US20250038009A1
公开(公告)日:2025-01-30
申请号:US18361747
申请日:2023-07-28
Applicant: Texas Instruments Incorporated
Inventor: Kengo Aoya , Masamitsu Matsuura , Daiki Komatsu
IPC: H01L21/48 , H01L21/56 , H01L23/31 , H01L23/495
Abstract: A semiconductor package has a relief recess in the mold compound, extending around the perimeter over the leads. The relief recess has a relief width greater than a thickness of the leads under the relief recess. Top surfaces of the leads may be exposed at the relief recess, or may be covered by the mold compound under the relief recess. In both cases, a height difference between the mold compound under the relief recess and the leads under the relief recess is less than the thickness of the leads under the relief recess. A majority of exposed side faces of the leads are characteristic of sawn surfaces, which includes leads being free of vertical striations or having burrs along bottom edges. The semiconductor package is singulated by sawing through the leads.
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公开(公告)号:US20240379597A1
公开(公告)日:2024-11-14
申请号:US18777976
申请日:2024-07-19
Applicant: Texas Instruments Incorporated
Inventor: Masamitsu Matsuura , Daiki Komatsu
IPC: H01L23/00 , H01L23/31 , H01L23/528
Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.
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公开(公告)号:US11848244B2
公开(公告)日:2023-12-19
申请号:US17491394
申请日:2021-09-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Makoto Shibuya , Masamitsu Matsuura , Kengo Aoya
IPC: H01L23/31 , H01L23/528 , H01L23/00
CPC classification number: H01L23/3114 , H01L23/528 , H01L24/08 , H01L24/96 , H01L2224/08245 , H01L2224/08501
Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.
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公开(公告)号:US20230005881A1
公开(公告)日:2023-01-05
申请号:US17364769
申请日:2021-06-30
Applicant: Texas Instruments Incorporated
Inventor: Anindya Poddar , Mahmud Chowdhury , Hau Nguyen , Masamitsu Matsuura , Ting-Ta Yen
IPC: H01L23/00 , H01L23/498 , H01L23/31 , H01L21/56 , H01L25/065
Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.
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10.
公开(公告)号:US20150147845A1
公开(公告)日:2015-05-28
申请号:US14552548
申请日:2014-11-25
Applicant: Texas Instruments Incorporated
Inventor: Anindya Poddar , Mark Allen Gerber , Mutsumi Masumoto , Masamitsu Matsuura , Kengo Aoya , Takeshi Onogami
IPC: H01L25/00 , H01L21/304 , H01L21/683 , H01L21/3213 , H01L21/321 , H01L21/3105 , H01L21/768
CPC classification number: H01L21/561 , H01L21/4857 , H01L21/568 , H01L21/6836 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2221/68327 , H01L2221/68345 , H01L2224/04105 , H01L2924/12042 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.
Abstract translation: 本发明的实施例提供了一种用于形成双面嵌入式模具系统的方法。 该方法从起始材料开始,包括顶表面和底表面,多个通孔,多个电镀金属柱,冲压垫和加强件。 将表面平坦化以暴露所包含的金属,其不是从管芯附着垫DAP区域选择性地蚀刻以形成空腔。 通过使用光刻胶图案和电镀创建一个加强筋。 涂抹胶带。 附上一个模具 层压和研磨。 去除胶带。 形式重新分配层RDL和焊接掩模。 安装表面贴装器件。
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