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    LEADED SEMICONDUCTOR DEVICE PACKAGE
    2.
    发明申请
    LEADED SEMICONDUCTOR DEVICE PACKAGE 有权

    公开(公告)号：US20230068748A1

    公开(公告)日：2023-03-02

    申请号：US17462067

    申请日：2021-08-31

    Applicant: Texas Instruments Incorporated

    Inventor： Masamitsu Matsuura

    IPC: H01L23/495 ,  H01L23/482

    Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for receiving a semiconductor die, and having conductive leads spaced from the die pad; a semiconductor die mounted on the die pad, the semiconductor die having bond pads on an active surface configured for making electrical connections; electrical connections coupling the bond pads of the semiconductor die to the conductive leads; mold compound covering a portion of the package substrate, the semiconductor die, and the electrical connections, with the leads extending through the mold compound and having end portions exposed from the mold compound; and the leads having a first portion with a first width and extending with the first width from the mold compound to a second portion having a second width that greater than the first width.

    SEMICONDUCTOR PACKAGE WITH MULTILAYER MOLD
    3.
    发明申请
    SEMICONDUCTOR PACKAGE WITH MULTILAYER MOLD 审中-公开

    公开(公告)号：US20200058570A1

    公开(公告)日：2020-02-20

    申请号：US16540943

    申请日：2019-08-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kengo Aoya ,  Masamitsu Matsuura ,  Takeshi Onogami ,  Hideaki Matsunaga

    IPC: H01L23/31 ,  H01L23/16 ,  H01L23/498 ,  H01L23/053 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

    Abstract: A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.

    SENSOR ELECTRONIC DEVICE
    4.
    发明申请
    SENSOR ELECTRONIC DEVICE 有权

    公开(公告)号：US20250140626A1

    公开(公告)日：2025-05-01

    申请号：US18495837

    申请日：2023-10-27

    Applicant: Texas Instruments Incorporated

    Inventor： Masamitsu Matsuura ,  Daiki Komatsu ,  Kengo Aoya

    IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

    Abstract: An electronic device includes a package structure having opposite first and second sides, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, the first and second sides spaced along a third direction orthogonal to the first and second directions, and an opening extending into the first side along the third direction, a first semiconductor die having a first side exposed in the opening of the package structure and an opposite second side partially enclosed by the package structure, and a second semiconductor die electrically connected to the first semiconductor die, the second semiconductor die enclosed by the package structure and laterally spaced apart from the first semiconductor die.

    Conductive members atop semiconductor packages
    5.
    发明授权
    Conductive members atop semiconductor packages 有权

    公开(公告)号：US12272626B2

    公开(公告)日：2025-04-08

    申请号：US17683074

    申请日：2022-02-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya ,  Anindya Poddar

    IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

    Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.

    STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE
    6.
    发明申请
    STRESS RELIEF SAWN QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250038009A1

    公开(公告)日：2025-01-30

    申请号：US18361747

    申请日：2023-07-28

    Applicant: Texas Instruments Incorporated

    Inventor： Kengo Aoya ,  Masamitsu Matsuura ,  Daiki Komatsu

    IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

    Abstract: A semiconductor package has a relief recess in the mold compound, extending around the perimeter over the leads. The relief recess has a relief width greater than a thickness of the leads under the relief recess. Top surfaces of the leads may be exposed at the relief recess, or may be covered by the mold compound under the relief recess. In both cases, a height difference between the mold compound under the relief recess and the leads under the relief recess is less than the thickness of the leads under the relief recess. A majority of exposed side faces of the leads are characteristic of sawn surfaces, which includes leads being free of vertical striations or having burrs along bottom edges. The semiconductor package is singulated by sawing through the leads.

    WAFER CHIP SCALE PACKAGE
    7.
    发明申请
    WAFER CHIP SCALE PACKAGE 有权

    公开(公告)号：US20240379597A1

    公开(公告)日：2024-11-14

    申请号：US18777976

    申请日：2024-07-19

    Applicant: Texas Instruments Incorporated

    Inventor： Masamitsu Matsuura ,  Daiki Komatsu

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528

    Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.

    Leaded wafer chip scale packages
    8.
    发明授权
    Leaded wafer chip scale packages 有权

    公开(公告)号：US11848244B2

    公开(公告)日：2023-12-19

    申请号：US17491394

    申请日：2021-09-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya

    IPC: H01L23/31 ,  H01L23/528 ,  H01L23/00

    CPC classification number: H01L23/3114 ,  H01L23/528 ,  H01L24/08 ,  H01L24/96 ,  H01L2224/08245 ,  H01L2224/08501

    Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.

    PACKAGE FOR STRESS SENSITIVE COMPONENT AND SEMICONDUCTOR DEVICE
    9.
    发明申请
    PACKAGE FOR STRESS SENSITIVE COMPONENT AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230005881A1

    公开(公告)日：2023-01-05

    申请号：US17364769

    申请日：2021-06-30

    Applicant: Texas Instruments Incorporated

    Inventor： Anindya Poddar ,  Mahmud Chowdhury ,  Hau Nguyen ,  Masamitsu Matsuura ,  Ting-Ta Yen

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

    Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.

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