公开(公告)号：US10263085B2

公开(公告)日：2019-04-16

申请号：US15415995

申请日：2017-01-26

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Sameer Pendharkar ,  Hiroshi Yamasaki

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

公开(公告)号：US11355597B2

公开(公告)日：2022-06-07

申请号：US17153976

申请日：2021-01-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Tomomatsu ,  Sameer Pendharkar ,  Hiroshi Yamasaki

IPC: H01L23/48 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423 ,  H01L23/482 ,  H01L29/20

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

公开(公告)号：US10186589B2

公开(公告)日：2019-01-22

申请号：US15865746

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/41 ,  H01L29/45 ,  H01L29/49 ,  H01L27/06 ,  H01L29/417 ,  H01L29/778

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

公开(公告)号：US20180190778A1

公开(公告)日：2018-07-05

申请号：US15865746

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/778 ,  H01L27/06 ,  H01L29/417 ,  H01L29/20 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

公开(公告)号：US20230065509A1

公开(公告)日：2023-03-02

申请号：US17462743

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Hiroyuki Tomomatsu

IPC: H01L27/06 ,  H01L29/778 ,  H01L29/66 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.

公开(公告)号：US10903320B2

公开(公告)日：2021-01-26

申请号：US16383857

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Tomomatsu ,  Sameer Pendharkar ,  Hiroshi Yamasaki

IPC: H01L29/40 ,  H01L29/778 ,  H01L23/48 ,  H01L29/423 ,  H01L23/482 ,  H01L29/20

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

公开(公告)号：US09899484B1

公开(公告)日：2018-02-20

申请号：US15395015

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/41 ,  H01L29/45 ,  H01L29/49 ,  H01L27/06 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

公开(公告)号：US08754495B1

公开(公告)日：2014-06-17

申请号：US13871713

申请日：2013-04-26

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Motoaki Kusamaki ,  Kohichi Kubota ,  Yuta Masuda ,  Akihiro Sugihara ,  Hiroshi Sera Kitada ,  Takeshi Konno

IPC: H01L31/0232 ,  H01L31/042 ,  H01L27/144 ,  H01L27/146 ,  G11B7/131 ,  G11B7/00

CPC classification number: H01L27/1462 ,  H01L27/14643 ,  H01L27/14689

Abstract: A method of fabricating a photodiode array having different photodiode structures includes providing a semiconductor substrate having first and second diode areas including a bottom substrate portion doped with a first doping type, an intrinsic layer, and a top silicon layer doped with a second doping type. The second diode areas are implanted with the second doping type. A dopant concentration in the surface of the second diode areas is at least three times higher than in the first diode areas. The top silicon layer is thermally oxidized to form a thermal silicon oxide layer to provide a bottom Anti-Reflective Coating (ARC) layer. The second diode areas grow thermal silicon oxide thicker as compared to the first diode areas. A top ARC layer is deposited on the bottom ARC layer. First PDs are provided in the first diode areas and second PDs provided in the second diode areas.

Abstract translation: 制造具有不同光电二极管结构的光电二极管阵列的方法包括提供具有第一和第二二极管区域的半导体衬底，该第二和第二二极管区域包括掺杂有第一掺杂类型，本征层和掺杂有第二掺杂类型的顶部硅层的底部衬底部分。 第二二极管区域被注入第二掺杂类型。 第二二极管区域的表面中的掺杂剂浓度比第一二极管区域的至少高三倍。 顶部硅层被热氧化以形成热氧化硅层，以提供底部抗反射涂层（ARC）层。 与第一二极管区域相比，第二二极管区域增加热氧化硅更厚。 顶部ARC层沉积在底部ARC层上。 在第二二极管区域提供第一PD，并且在第二二极管区域中提供第二PD。

公开(公告)号：US12211835B2

公开(公告)日：2025-01-28

申请号：US17462743

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Hiroyuki Tomomatsu

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/66 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.

公开(公告)号：US20210143258A1

公开(公告)日：2021-05-13

申请号：US17153976

申请日：2021-01-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Tomomatsu ,  Sameer Pendharkar ,  Hiroshi Yamasaki

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/423 ,  H01L23/482

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.