公开(公告)号：US20180323790A1

公开(公告)日：2018-11-08

申请号：US16036221

申请日：2018-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun DUSAD ,  Visvesvaraya PENTAKOTA ,  Mark Baxter WEAVER ,  William BRIGHT ,  Jiankun HU

IPC: H03L7/08

CPC classification number: H03L7/08 ,  G06F1/12 ,  H03L7/16

Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.

公开(公告)号：US20230006681A1

公开(公告)日：2023-01-05

申请号：US17931165

申请日：2022-09-12

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ganapat GHOTGALKAR ,  Wei FU ,  Venkatseema DAS ,  Jiankun HU

IPC: H03L7/089 ,  H03L7/095 ,  H03L7/087

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

公开(公告)号：US20210384913A1

公开(公告)日：2021-12-09

申请号：US17458001

申请日：2021-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailesh Ganapat GHOTGALKAR ,  Wei FU ,  Venkatseema DAS ,  Jiankun HU

IPC: H03L7/089 ,  H03L7/095 ,  H03L7/087

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

公开(公告)号：US20180191355A1

公开(公告)日：2018-07-05

申请号：US15395489

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun DUSAD ,  Visvesvaraya PENTAKOTA ,  Mark Baxter WEAVER ,  William BRIGHT ,  Jiankun HU

IPC: H03L7/08

CPC classification number: H03L7/08

Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.