公开(公告)号：US20200252076A1

公开(公告)日：2020-08-06

申请号：US16856167

申请日：2020-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya PENTAKOTA

IPC: H03M1/20

Abstract: A method of converting an analog signal to a digital code, comprising: using a first comparator to receive an input signal and a first comparison signal, and to generate a first output as a function of the input signal and the first comparison signal; using a second comparator to receive the input signal and a second comparison signal, and to generate a second output as a function of the input signal and the second comparison signal; and using an interpolation comparator to receive the first and second outputs, and to generate a third output based on relative timing of the first and second outputs; further including multiplexing to permit a second-level comparator to receive timing signals from the interpolation comparator and only one of two dummy comparators.

公开(公告)号：US20190273601A1

公开(公告)日：2019-09-05

申请号：US16417827

申请日：2019-05-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh BALAKRISHNAN ,  Shagun DUSAD ,  Visvesvaraya PENTAKOTA ,  Srinivas Kumar Reddy NARU ,  Sarma Sundareswara GUNTURI ,  Nagalinga Swamy Basayya AREMALLAPUR

IPC: H04L7/00 ,  H03K5/14

Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

公开(公告)号：US20180191355A1

公开(公告)日：2018-07-05

申请号：US15395489

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun DUSAD ,  Visvesvaraya PENTAKOTA ,  Mark Baxter WEAVER ,  William BRIGHT ,  Jiankun HU

IPC: H03L7/08

CPC classification number: H03L7/08

Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.

公开(公告)号：US20160315629A1

公开(公告)日：2016-10-27

申请号：US14871373

申请日：2015-09-30

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy NARU ,  Nagarajan VISWANATHAN ,  Visvesvaraya PENTAKOTA

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/36 ,  H03M1/00

CPC classification number: H03M1/0609 ,  H03M1/203 ,  H03M1/361

Abstract: In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.

Abstract translation: 在所描述的示例中，模数转换器（ADC）包括主ADC和参考ADC。 主ADC响应于输入信号产生区域信息信号和数字输出。 参考ADC从主ADC接收多个参考电压。 多个参考电压包括第一参考电压和第二参考电压。 参考ADC根据输入信号，第一参考电压和第二参考电压产生参考输出。 减法器响应于数字输出和参考输出产生一个误差信号。 响应于区域信息信号，误差信号和参考输出，逻辑块产生第一偏移校正信号，第二偏移校正信号和增益失配信号中的一个。

公开(公告)号：US20210336630A1

公开(公告)日：2021-10-28

申请号：US17366506

申请日：2021-07-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya PENTAKOTA

IPC: H03M1/20

Abstract: An analog-to-digital converter (ADC) including: a signal input adapted to receive an analog signal; a first reference voltage input adapted to receive a first reference voltage; a second reference voltage input adapted to receive a second reference voltage, the second reference voltage is different than the first reference voltage; a first delay circuit having a first delay input coupled to the signal input, a second delay input coupled to the first reference voltage input, a first delay output and a second delay output; a second delay circuit having a third delay input coupled to the signal input, a fourth delay input coupled to the second reference voltage input; a third delay output and a fourth delay output; a first comparator having a first comparator input coupled to the first delay output, a second comparator input coupled to the second delay output and a first comparator output; and a second comparator having a third comparator input coupled to the third delay output, a fourth comparator input coupled to the fourth delay output and a second comparator output.

公开(公告)号：US20190222207A1

公开(公告)日：2019-07-18

申请号：US16364239

申请日：2019-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya PENTAKOTA

IPC: H03K5/24 ,  H03M1/50

CPC classification number: H03K5/249 ,  H03K2005/00215 ,  H03M1/50

Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

公开(公告)号：US20180323790A1

公开(公告)日：2018-11-08

申请号：US16036221

申请日：2018-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun DUSAD ,  Visvesvaraya PENTAKOTA ,  Mark Baxter WEAVER ,  William BRIGHT ,  Jiankun HU

IPC: H03L7/08

CPC classification number: H03L7/08 ,  G06F1/12 ,  H03L7/16

Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.

公开(公告)号：US20170041014A1

公开(公告)日：2017-02-09

申请号：US15048027

申请日：2016-02-19

Applicant: Texas Instruments Incorporated

Inventor： Neeraj SHRIVASTAVA ,  Supreet JOSHI ,  Himanshu VARSHNEY ,  Jafar Sadique KAVILADATH ,  Visvesvaraya PENTAKOTA ,  Shagun DUSAD

IPC: H03M1/10 ,  H03M1/74 ,  H03M1/78

CPC classification number: H03M1/1009 ,  H03M1/1019 ,  H03M1/1057 ,  H03M1/66 ,  H03M1/742 ,  H03M1/745 ,  H03M1/785

Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

Abstract translation: 本公开提供了包括多个DAC元件的电流转向数模转换器（DAC）。 多个DAC元件中的至少一个DAC元件耦合到校准电路。 校准电路包括通过第一估计开关耦合到DAC元件的主节点的固定电流源。 数字码发生器耦合到主节点，并且产生对应于在主节点处产生的主电压的第一数字码。 数字代码生成器产生第二数字代码。 校正DAC耦合到数字代码发生器并且基于第二数字代码产生偏置电压。 偏置电压被提供给DAC元件，使得流过多个DAC元件中的每个DAC元件的电流相等。

公开(公告)号：US20210184665A1

公开(公告)日：2021-06-17

申请号：US17181073

申请日：2021-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishi SOUNDARARAJAN ,  Visvesvaraya PENTAKOTA

IPC: H03K5/24 ,  H03M1/50

Abstract: An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.

公开(公告)号：US20200177168A1

公开(公告)日：2020-06-04

申请号：US16396873

申请日：2019-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nagalinga Swamy Basayya AREMALLAPUR ,  Eeshan MIGLANI ,  Visvesvaraya PENTAKOTA ,  Praxal Sunilkumar SHAH

IPC: H03K3/013 ,  H03K21/10 ,  H03K3/037

Abstract: A spur cancellation circuit for use in a mixed signal circuit. A spur cancellation circuit includes a clock generation circuit, a flip-flop bank, and a control circuit. The clock generation circuit is configured to generate a clock signal. The flip-flop bank is coupled to the clock generation circuit, and includes a plurality of flip-flops configured to be clocked by the clock signal. The control circuit is coupled to the clock generation circuit and the flip-flop bank. The control circuit is configured to individually enable one or more of the flip-flops to change state responsive to the clock signal and consume a predetermined amount of power; and to provide a data value to be clocked into the flip-flops.