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    Package on package memory interface and configuration with error code correction
    1.
    发明授权
    Package on package memory interface and configuration with error code correction 有权

    公开(公告)号：US10089172B2

    公开(公告)日：2018-10-02

    申请号：US14587878

    申请日：2014-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

    IPC: G06F11/10 ,  G11C29/52

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

    Package on package memory interface and configuration with error code correction
    2.
    发明授权
    Package on package memory interface and configuration with error code correction 有权

    公开(公告)号：US11662211B2

    公开(公告)日：2023-05-30

    申请号：US16983437

    申请日：2020-08-03

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

    IPC: G01C21/20 ,  G06F11/10

    CPC classification number: G01C21/206 ,  G06F11/10 ,  G06F2201/845

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

    Package On Package Memory Interface and Configuration With Error Code Correction
    4.
    发明公开
    Package On Package Memory Interface and Configuration With Error Code Correction 审中-公开

    公开(公告)号：US20230258454A1

    公开(公告)日：2023-08-17

    申请号：US18306510

    申请日：2023-04-25

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

    IPC: G01C21/20 ,  G06F11/10

    CPC classification number: G01C21/206 ,  G06F11/10 ,  G06F2201/845

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

    Package On Package Memory Interface and Configuration With Error Code Correction
    6.
    发明申请
    Package On Package Memory Interface and Configuration With Error Code Correction 审中-公开
    包装封装内存接口和配置与错误代码校正

    公开(公告)号：US20150227421A1

    公开(公告)日：2015-08-13

    申请号：US14587878

    申请日：2014-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Moody

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/10 ,  G06F2201/845

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

    Abstract translation: 信息通信电路，包括用于在封装配置上耦合到封装中的第二集成电路的第一集成电路。 第一集成电路包括用于传送信息位的处理电路，并且信息位包括数据位和纠错位，其中纠错位用于指示数据位是否被正确接收。 第二集成电路包括用于接收和存储至少一些信息位的存储器。 信息通信电路还包括接口电路，用于沿着多个导体选择性地在封装配置上的封装之间通信。 在第一种情况下，接口电路仅选择性地仅沿导体数传送数据位。 在第二种情况下，接口电路沿着导体数量的第二组和第二组导体选择性地传送沿导体数量和误差校正位的第一组的数据位。

    Package on package memory interface and configuration with error code correction
    8.
    发明授权
    Package on package memory interface and configuration with error code correction 有权

    公开(公告)号：US10767998B2

    公开(公告)日：2020-09-08

    申请号：US16114419

    申请日：2018-08-28

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

    IPC: G01C21/20 ,  G06F11/10

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

    Package On Package Memory Interface and Configuration With Error Code Correction
    9.
    发明申请
    Package On Package Memory Interface and Configuration With Error Code Correction 审中-公开

    公开(公告)号：US20180364051A1

    公开(公告)日：2018-12-20

    申请号：US16114419

    申请日：2018-08-28

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Moody

    IPC: G01C21/20

    CPC classification number: G01C21/206 ,  G06F11/10 ,  G06F2201/845

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

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