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    Package on package memory interface and configuration with error code correction
    1.
    发明授权
    Package on package memory interface and configuration with error code correction 有权

    公开(公告)号：US11662211B2

    公开(公告)日：2023-05-30

    申请号：US16983437

    申请日：2020-08-03

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

    IPC: G01C21/20 ,  G06F11/10

    CPC classification number: G01C21/206 ,  G06F11/10 ,  G06F2201/845

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

    Package On Package Memory Interface and Configuration With Error Code Correction
    2.
    发明公开
    Package On Package Memory Interface and Configuration With Error Code Correction 审中-公开

    公开(公告)号：US20230258454A1

    公开(公告)日：2023-08-17

    申请号：US18306510

    申请日：2023-04-25

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

    IPC: G01C21/20 ,  G06F11/10

    CPC classification number: G01C21/206 ,  G06F11/10 ,  G06F2201/845

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

    Ensuring Imaging Subsystem Integrity in Camera Based Safety Systems
    4.
    发明申请
    Ensuring Imaging Subsystem Integrity in Camera Based Safety Systems 有权
    确保摄像机安全系统中的成像子系统完整性

    公开(公告)号：US20150304648A1

    公开(公告)日：2015-10-22

    申请号：US14607053

    申请日：2015-01-27

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Vasant Easwaran ,  Mihir Narendra Mody ,  Prashant Dinkar Karandikar ,  Prithvi Y.A. Shankar ,  Aishwarya Dubey ,  Kedar Chitnis ,  Rajat Sagar

    IPC: H04N17/00 ,  G06T7/00

    CPC classification number: H04N17/002 ,  G06T7/0002 ,  G06T2207/30168 ,  G06T2207/30252

    Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.

    Abstract translation: 提供了一种用于测试片上系统（SOC）的成像子系统的方法，其包括在所述SOC的处理器上周期性地执行成像子系统测试软件指令，响应于所述成像子系统的执行而接收所述成像子系统中的参考图像数据 测试软件指令，由成像子系统对参考图像数据执行图像信号处理，以生成经处理的参考图像数据，以及通过测试软件指令使用经处理的参考图像数据来验证成像子系统是否正确地操作。

    Package On Package Memory Interface and Configuration With Error Code Correction
    5.
    发明申请
    Package On Package Memory Interface and Configuration With Error Code Correction 审中-公开
    包装封装内存接口和配置与错误代码校正

    公开(公告)号：US20150227421A1

    公开(公告)日：2015-08-13

    申请号：US14587878

    申请日：2014-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Moody

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/10 ,  G06F2201/845

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

    Abstract translation: 信息通信电路，包括用于在封装配置上耦合到封装中的第二集成电路的第一集成电路。 第一集成电路包括用于传送信息位的处理电路，并且信息位包括数据位和纠错位，其中纠错位用于指示数据位是否被正确接收。 第二集成电路包括用于接收和存储至少一些信息位的存储器。 信息通信电路还包括接口电路，用于沿着多个导体选择性地在封装配置上的封装之间通信。 在第一种情况下，接口电路仅选择性地仅沿导体数传送数据位。 在第二种情况下，接口电路沿着导体数量的第二组和第二组导体选择性地传送沿导体数量和误差校正位的第一组的数据位。

    Package on package memory interface and configuration with error code correction
    7.
    发明授权
    Package on package memory interface and configuration with error code correction 有权

    公开(公告)号：US10089172B2

    公开(公告)日：2018-10-02

    申请号：US14587878

    申请日：2014-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

    IPC: G06F11/10 ,  G11C29/52

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

    SYSTEM AND METHOD FOR MANAGING CACHE
    9.
    发明申请
    SYSTEM AND METHOD FOR MANAGING CACHE 有权
    用于管理缓存的系统和方法

    公开(公告)号：US20150339234A1

    公开(公告)日：2015-11-26

    申请号：US14583020

    申请日：2014-12-24

    Applicant: Texas Instruments Incorporated

    Inventor： Prashant Dinkar Karandikar ,  Mihir Mody ,  Hetul Sanghavi ,  Vasant Easwaran ,  Prithvi Y.A. Shankar ,  Rahul Gulati ,  Niraj Nandan ,  Subrangshu Das

    IPC: G06F12/08

    CPC classification number: G06F12/0862 ,  G06F3/06 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/601 ,  G06F2212/602

    Abstract: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.

    Abstract translation: 系统包括第一和第二处理组件，基于限定的分离器组件，第一和第二可配置高速缓存元件和仲裁器组件。 第一数据处理组件在存储器内的第一位置处生成对数据的第一部分的第一请求。 第二数据处理组件在存储器内的第二位置产生第二数据部分的第二请求。 基于限定符的分离器组件基于限定符路由第一请求和第二请求。 第一可配置缓存元件启用或禁用在存储器的第一区域内的预取数据。 第二可配置高速缓存元件在存储器的第二区域内启用或禁用预取数据。 仲裁器组件将第一个请求和第二个请求路由到内存。

    Package on package memory interface and configuration with error code correction
    10.
    发明授权
    Package on package memory interface and configuration with error code correction 有权

    公开(公告)号：US10767998B2

    公开(公告)日：2020-09-08

    申请号：US16114419

    申请日：2018-08-28

    Applicant: Texas Instruments Incorporated

    Inventor： Rahul Gulati ,  Aishwarya Dubey ,  Nainala Vyagrheswarudu ,  Vasant Easwaran ,  Prashant Dinkar Karandikar ,  Mihir Mody

    IPC: G01C21/20 ,  G06F11/10

    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

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