公开(公告)号：US20240258927A1

公开(公告)日：2024-08-01

申请号：US18160374

申请日：2023-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bharath Balaji Kannan ,  Robert Martinez ,  Jose Antonio Vieira Formenti ,  Michael Corry

IPC: H02M3/335 ,  B60L53/22 ,  H02M1/08 ,  H02M7/5387 ,  H02P27/06

CPC classification number: H02M3/335 ,  B60L53/22 ,  H02M1/08 ,  H02M7/5387 ,  H02P27/06 ,  B60L2210/10

Abstract: A DC-to-DC converter having primary- and secondary-side circuitry separated by an isolation barrier, with a transformer and a feedback lane across the barrier, uses a dynamic function current source in its secondary-side circuitry to dynamically adjust the hysteresis threshold only at the transformer burst turn-off edge to provide enhanced immunity to transformer switching noise. An output voltage of the converter (or signal based thereon) is compared to the threshold to provide an input to a timing pulse generator that closes a switch to couple the dynamic function current source into voltage threshold setting circuitry. The dynamic function current source can reduce the threshold to a level that avoids chattering in transformer burst turn-off feedback signal caused by the noise, for a duration that can be based on lane delay of the converter and to an amplitude that can be based on the expected maximum negative amplitude of the noise.

公开(公告)号：US11967566B2

公开(公告)日：2024-04-23

申请号：US18086610

申请日：2022-12-21

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaxmi Gumaste Khanolkar ,  Robert Martinez ,  Zhemin Zhang ,  Yongbin Chu

IPC: H01L23/552 ,  H01F27/28 ,  H01L21/56 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01F27/2804 ,  H01L21/56 ,  H01L23/49575 ,  H01L25/50 ,  H01F2027/2809

Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.

公开(公告)号：US20230402930A1

公开(公告)日：2023-12-14

申请号：US17827447

申请日：2022-05-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Corry ,  Jose V. Formenti ,  Robert Martinez

IPC: H02M3/335 ,  H02M1/36

CPC classification number: H02M3/33573 ,  H02M1/36

Abstract: In some examples, an apparatus includes: a power stage having a power stage voltage input, a power stage control input, and a power stage output; a controller having a power stage control output coupled to the power stage control input, an output voltage status terminal, and a status signal input; a transformer having a primary side coil coupled to the power stage output, and a secondary side coil; a feedback voltage processor having a feedback input coupled to the secondary side coil, and a feedback output; a control message generator having a control input coupled to the secondary side coil, and a control message output; a status signal generator having first and second signal inputs coupled to respective feedback and control message outputs, and a status signal output; and a communication channel device coupled between the status signal input and output.

公开(公告)号：US20230207483A1

公开(公告)日：2023-06-29

申请号：US18086610

申请日：2022-12-21

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaxmi Gumaste Khanolkar ,  Robert Martinez ,  Zhemin Zhang ,  Yongbin Chu

IPC: H01L23/552 ,  H01L23/495 ,  H01L21/56 ,  H01F27/28 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01F27/2804 ,  H01L21/56 ,  H01L23/49575 ,  H01L25/50 ,  H01F2027/2809

Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.

公开(公告)号：US20200303319A1

公开(公告)日：2020-09-24

申请号：US16800043

申请日：2020-02-25

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaxmi Gumaste Khanolkar ,  Robert Martinez ,  Zhemin Zhang ,  Yongbin Chu

IPC: H01L23/552 ,  H01L23/495 ,  H01L25/00 ,  H01L21/56 ,  H01F27/28

Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.

公开(公告)号：US11538766B2

公开(公告)日：2022-12-27

申请号：US16800043

申请日：2020-02-25

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaxmi Gumaste Khanolkar ,  Robert Martinez ,  Zhemin Zhang ,  Yongbin Chu

IPC: H01L23/552 ,  H01L23/495 ,  H01L21/56 ,  H01F27/28 ,  H01L25/00

Abstract: A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.