Multiple dithering profile signal generation

    公开(公告)号:US12051973B2

    公开(公告)日:2024-07-30

    申请号:US17459928

    申请日:2021-08-27

    CPC classification number: H02M3/156 H02M1/44 H04B1/69

    Abstract: At least some aspects of the present disclosure provide for a system. In some examples, the system includes a pulse width modulation (PWM) generator configured to generate a PWM signal. The PWM generator generates the PWM signal by generating a first signal having a first dithering profile and a first frequency bandwidth, generating a second signal having a second dithering profile and a second frequency bandwidth greater than the first frequency bandwidth, modulating the second signal with the first signal to generate a dual random spread spectrum signal, and generating the pulse width modulation signal according to the dual random spread spectrum signal.

    METHODS AND APPARATUS FOR MULTI-PHASE CLOCK GENERATION

    公开(公告)号:US20250007521A1

    公开(公告)日:2025-01-02

    申请号:US18215716

    申请日:2023-06-28

    Abstract: An example apparatus includes: first clock generation circuitry including: interlock circuitry having a terminal; reference clock generation circuitry having a first terminal and a second terminal, the first terminal of the reference clock generation circuitry coupled to the terminal of the interlock circuitry; first duty cycle replication circuitry having a first terminal and a second terminal, the first terminal of the first duty cycle replication circuitry coupled to the second terminal of the reference clock generation circuitry; and buffer circuitry having a first terminal and a second terminal, the first terminal of the buffer circuitry coupled to the second terminal of the first duty cycle replication circuitry; and second clock generation circuitry including: detection circuitry having a first terminal and a second terminal, the first terminal of the detection circuitry coupled to the second terminal of the buffer circuitry; second detection circuitry having a first terminal and a second terminal.

    DC to DC converter and PWM controller with adaptive compensation circuit
    3.
    发明授权
    DC to DC converter and PWM controller with adaptive compensation circuit 有权
    DC至DC转换器和具有自适应补偿电路的PWM控制器

    公开(公告)号:US09325233B2

    公开(公告)日:2016-04-26

    申请号:US14320747

    申请日:2014-07-01

    Abstract: DC to DC converters and PWM controllers are presented in which a slope compensation ramp signal is provided for current control operation via a frequency adaptive compensation circuit with a phase locked loop that provides a control output signal having an amplitude generally proportional to the frequency of a clock signal, and a slope generator circuit generating the slope compensation ramp signal with an amplitude generally proportional to the control output signal amplitude.

    Abstract translation: 提供DC到DC转换器和PWM控制器,其中通过具有锁相环的频率自适应补偿电路提供斜率补偿斜坡信号用于电流控制操作,该锁相环提供具有与时钟频率成正比的幅度的控制输出信号 信号和斜率发生器电路,其产生具有与控制输出信号幅度成正比的幅度的斜坡补偿斜坡信号。

    DC TO DC CONVERTER AND PWM CONTROLLER WITH ADAPTIVE COMPENSATION CIRCUIT
    4.
    发明申请
    DC TO DC CONVERTER AND PWM CONTROLLER WITH ADAPTIVE COMPENSATION CIRCUIT 有权
    直流到直流转换器和PWM控制器与自适应补偿电路

    公开(公告)号:US20160006336A1

    公开(公告)日:2016-01-07

    申请号:US14320747

    申请日:2014-07-01

    Abstract: DC to DC converters and PWM controllers are presented in which a slope compensation ramp signal is provided for current control operation via a frequency adaptive compensation circuit with a phase locked loop that provides a control output signal having an amplitude generally proportional to the frequency of a clock signal, and a slope generator circuit generating the slope compensation ramp signal with an amplitude generally proportional to the control output signal amplitude.

    Abstract translation: 提供DC到DC转换器和PWM控制器,其中通过具有锁相环的频率自适应补偿电路提供斜率补偿斜坡信号用于电流控制操作,该锁相环提供具有与时钟频率成正比的幅度的控制输出信号 信号和斜率发生器电路,其产生具有与控制输出信号幅度成正比的幅度的斜坡补偿斜坡信号。

    Wide input voltage low IQ switching converter

    公开(公告)号:US11349393B2

    公开(公告)日:2022-05-31

    申请号:US16996207

    申请日:2020-08-18

    Abstract: A system has an input voltage source, a power stage coupled to the input voltage source, a load coupled to an output node of the power stage and a control circuit, the control circuit implemented on a semiconductor die and including: an error amplifier having a first input, a second input and an output; a voltage divider coupled to the output node and configured to provide an output voltage sense value to the first input of the error amplifier; and a programmable reference voltage circuit with an output coupled to the second input of the error amplifier. The programmable reference voltage circuit includes: a reference voltage source; scaling circuit components between the reference voltage source and the second input of the error amplifier; and a switch between the reference voltage source and the second input of the error amplifier. The control circuit is coupled to the power stage and is configured to generate a control signal for switches of the power stage.

    Multiple dithering profile signal generation

    公开(公告)号:US11152855B2

    公开(公告)日:2021-10-19

    申请号:US16779175

    申请日:2020-01-31

    Abstract: At least some aspects of the present disclosure provide for a system. In some examples, the system includes a pulse width modulation (PWM) generator configured to generate a PWM signal. The PWM generator generates the PWM signal by generating a first signal having a first dithering profile and a first frequency bandwidth, generating a second signal having a second dithering profile and a second frequency bandwidth greater than the first frequency bandwidth, modulating the second signal with the first signal to generate a dual random spread spectrum signal, and generating the pulse width modulation signal according to the dual random spread spectrum signal.

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