Abstract:
At least some aspects of the present disclosure provide for a system. In some examples, the system includes a pulse width modulation (PWM) generator configured to generate a PWM signal. The PWM generator generates the PWM signal by generating a first signal having a first dithering profile and a first frequency bandwidth, generating a second signal having a second dithering profile and a second frequency bandwidth greater than the first frequency bandwidth, modulating the second signal with the first signal to generate a dual random spread spectrum signal, and generating the pulse width modulation signal according to the dual random spread spectrum signal.
Abstract:
An example apparatus includes: first clock generation circuitry including: interlock circuitry having a terminal; reference clock generation circuitry having a first terminal and a second terminal, the first terminal of the reference clock generation circuitry coupled to the terminal of the interlock circuitry; first duty cycle replication circuitry having a first terminal and a second terminal, the first terminal of the first duty cycle replication circuitry coupled to the second terminal of the reference clock generation circuitry; and buffer circuitry having a first terminal and a second terminal, the first terminal of the buffer circuitry coupled to the second terminal of the first duty cycle replication circuitry; and second clock generation circuitry including: detection circuitry having a first terminal and a second terminal, the first terminal of the detection circuitry coupled to the second terminal of the buffer circuitry; second detection circuitry having a first terminal and a second terminal.
Abstract:
DC to DC converters and PWM controllers are presented in which a slope compensation ramp signal is provided for current control operation via a frequency adaptive compensation circuit with a phase locked loop that provides a control output signal having an amplitude generally proportional to the frequency of a clock signal, and a slope generator circuit generating the slope compensation ramp signal with an amplitude generally proportional to the control output signal amplitude.
Abstract:
DC to DC converters and PWM controllers are presented in which a slope compensation ramp signal is provided for current control operation via a frequency adaptive compensation circuit with a phase locked loop that provides a control output signal having an amplitude generally proportional to the frequency of a clock signal, and a slope generator circuit generating the slope compensation ramp signal with an amplitude generally proportional to the control output signal amplitude.
Abstract:
A system has an input voltage source, a power stage coupled to the input voltage source, a load coupled to an output node of the power stage and a control circuit, the control circuit implemented on a semiconductor die and including: an error amplifier having a first input, a second input and an output; a voltage divider coupled to the output node and configured to provide an output voltage sense value to the first input of the error amplifier; and a programmable reference voltage circuit with an output coupled to the second input of the error amplifier. The programmable reference voltage circuit includes: a reference voltage source; scaling circuit components between the reference voltage source and the second input of the error amplifier; and a switch between the reference voltage source and the second input of the error amplifier. The control circuit is coupled to the power stage and is configured to generate a control signal for switches of the power stage.
Abstract:
At least some aspects of the present disclosure provide for a system. In some examples, the system includes a pulse width modulation (PWM) generator configured to generate a PWM signal. The PWM generator generates the PWM signal by generating a first signal having a first dithering profile and a first frequency bandwidth, generating a second signal having a second dithering profile and a second frequency bandwidth greater than the first frequency bandwidth, modulating the second signal with the first signal to generate a dual random spread spectrum signal, and generating the pulse width modulation signal according to the dual random spread spectrum signal.