公开(公告)号：US20230238291A1

公开(公告)日：2023-07-27

申请号：US17736549

申请日：2022-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shuqian Huang ,  Sheng Zou ,  Yuchen Li ,  Peng Li ,  Chao Zhuang ,  Zhiyun Liu

IPC: H01L21/66 ,  G05B19/418

CPC classification number: H01L22/20 ,  G05B19/4185 ,  G05B2219/40066

Abstract: The present disclosure generally relates to determining a process condition in a semiconductor process using attribute-relative process conditions. An example is a method of forming an integrated circuit (IC). First and second historical process conditions are obtained. The first historical process conditions are of previous semiconductor processing corresponding to a target value of a process attribute for forming the IC, and the second historical process conditions are of previous semiconductor processing corresponding to variable values of the process attribute. Attribute-relative process conditions are calculated. Each attribute-relative process condition is based on the first historical process conditions and the second historical process conditions that correspond to a respective given value of the variable values. An average process condition is determined from a subset of the attribute-relative process conditions. A process condition of a subsequent semiconductor process is set based on the average process condition.

公开(公告)号：US10903345B2

公开(公告)日：2021-01-26

申请号：US15831112

申请日：2017-12-04

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Ho Lin ,  Tianping Lv ,  Sheng Zou ,  Qiuling Jia

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L21/74 ,  H01L23/485 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/06

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

公开(公告)号：US09865718B1

公开(公告)日：2018-01-09

申请号：US15342896

申请日：2016-11-03

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Ho Lin ,  Tian Ping Lv ,  Sheng Zou ,  Qiu Ling Jia

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/78 ,  H01L21/283 ,  H01L21/3213

CPC classification number: H01L29/7397 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/0653 ,  H01L29/7827

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.